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32 33 34 35
36
37 import ti.sdo.utils.MultiProc;
38
39 /*!
40 * ======== InterruptIpu ========
41 * IPU interrupt manager
42 */
43
44 @ModuleStartup
45
46 module InterruptIpu inherits ti.sdo.ipc.notifyDrivers.IInterrupt
47 {
48 /*!
49 * Maximum number of cores
50 *
51 * @_nodoc
52 */
53 const UInt8 NUM_CORES = 11;
54
55 /*!
56 * Maximum number of EVE cores
57 *
58 * Although your device may have fewer EVE cores, `NUM_EVES` represents
59 * the maximum number of EVEs that may be present on a Vayu system.
60 */
61 const UInt8 NUM_EVES = 4;
62
63 /*!
64 * Maximum number of IPU cores
65 *
66 * @_nodoc
67 */
68 const UInt8 NUM_Ipu_CORES = 2;
69
70 /*!
71 * Number of internal EVE mailboxes
72 *
73 * Each EVE core has 3 mailboxes.
74 *
75 * Although your device may have fewer EVE cores, `NUM_EVE_MBX` represents
76 * the maximum number of EVE mailboxes (including all EVE cores) that may
77 * be present.
78 */
79 const UInt8 NUM_EVE_MBX = NUM_EVES * 3;
80
81 /*!
82 * Number of System mailboxes used by IPC
83 *
84 * This represents the number of System mailboxes used by IPC. IPC
85 * currently uses system mailboxes 5, 6, 7 and 8.
86 */
87 const UInt8 NUM_SYS_MBX = 4;
88
89 /*!
90 * Base address for the mailbox subsystems
91 *
92 * The `mailboxBaseAddr` array indicates the virtual addresses through
93 * which IPC will access various mailboxes. The specific mailbox addresses
94 * each array index maps to follows:
95 * @p(blist)
96 * - 0 - EVE1 MBX0
97 * - 1 - EVE1 MBX1
98 * - 2 - EVE1 MBX2 (unused, do not assign)
99 * - 3 - EVE2 MBX0
100 * - 4 - EVE2 MBX1
101 * - 5 - EVE2 MBX2 (unused, do not assign)
102 * - 6 - EVE3 MBX0
103 * - 7 - EVE3 MBX1
104 * - 8 - EVE1 MBX2 (unused, do not assign)
105 * - 9 - EVE4 MBX0
106 * - 10 - EVE4 MBX1
107 * - 11 - EVE1 MBX2 (unused, do not assign)
108 * - 12 - System Mailbox 5
109 * - 13 - System Mailbox 6
110 * - 14 - System Mailbox 7
111 * - 15 - System Mailbox 8
112 * @p
113 *
114 * Note that these mailboxes are not accessible at their physical
115 * addresses (in the 0x4XXX_XXXX range). So default virtual addresses
116 * through which these mailboxes will be accessed are assigned in the
117 * 0x6XXX_XXXX range. Users must ensure these virtual addresses are
118 * correctly mapped to the 0x4XXX_XXXX-based phys addrs in each IPUs AMMU.
119 */
120 config UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
121
122 /*!
123 * Mailbox table for storing encoded Base Address, mailbox user Id,
124 * and sub-mailbox index.
125 *
126 * @_nodoc
127 */
128 config UInt32 mailboxTable[NUM_CORES * NUM_CORES];
129
130 /*!
131 * Base address for the Ducati CTRL register
132 */
133 config UInt32 ducatiCtrlBaseAddr = 0x40001000;
134
135 /*!
136 * Processor Id table
137 *
138 * @_nodoc
139 */
140 config UInt32 procIdTable[NUM_CORES];
141
142 internal:
143
144 /*! Statically retrieve procIds to avoid doing this at runtime */
145 config UInt eve1ProcId = MultiProc.INVALIDID;
146 config UInt eve2ProcId = MultiProc.INVALIDID;
147 config UInt eve3ProcId = MultiProc.INVALIDID;
148 config UInt eve4ProcId = MultiProc.INVALIDID;
149 config UInt dsp1ProcId = MultiProc.INVALIDID;
150 config UInt dsp2ProcId = MultiProc.INVALIDID;
151 config UInt ipu1_0ProcId = MultiProc.INVALIDID;
152 config UInt ipu2_0ProcId = MultiProc.INVALIDID;
153 config UInt hostProcId = MultiProc.INVALIDID;
154 config UInt ipu1_1ProcId = MultiProc.INVALIDID;
155 config UInt ipu2_1ProcId = MultiProc.INVALIDID;
156
157 /*! Function table */
158 struct FxnTable {
159 Fxn func;
160 UArg arg;
161 }
162
163 /*! Stub to be plugged for inter-ducati interrupts */
164 Void intShmDucatiStub(UArg arg);
165
166 /*! Stub to be plugged for intra-ducati interrupts */
167 Void intShmMbxStub(UArg arg);
168
169 struct Module_State {
170 171 172 173
174 FxnTable fxnTable[NUM_CORES];
175
176
177 UInt16 numPlugged[NUM_EVE_MBX + NUM_SYS_MBX];
178
179
180 UInt16 interruptTable[NUM_CORES];
181 };
182 }