DMAN3_Params Struct Reference
[DMAN3]

The module configuration structure for DMAN3 implementation. It is set at design time by the system integrator to ensure optimal sharing of DMA resources for the execution environment. More...

#include <dman3.h>

Data Fields

Uns * qdmaPaRamBase
 Physical base address of the PARAM0 in the EDMA3/QDMA hardware whose resources are being managed by DMAN3.
Uns maxPaRamEntries
 Total number of PARAM Table entries on the hardware (eg, for IVA2 this is 128, for Himalaya, this is 256).
Uns paRamBaseIndex
 Represents the first PARAM TABLE ENTRY NUMBER that is assigned by configuration for exclusive DMAN3 allocation.
Uns numPaRamEntries
 Number of PARAM Table entries starting at DMAN3_PARAM_BASE_INDEX assigned by configuration for exclusive DMAN3 allocation.
Uns maxQdmaChannels
 The total number of Physical QDMA channels available on the hardware.
Uns numQdmaChannels
 The number of Physical QDMA channels that are assigned to DMAN3 via configuration.
Uns * qdmaChannels
 Array of size DMAN3_NUM_QDMA_CHANNELS that will contain the channel numbers of the Physical QDMA channels assigned to DMAN3 via configuration.
Uns tccAllocationMaskH
 32-bit "high" bitmask representing configuration provided list of TCCs for exclusive DMAN3 allocation.
Uns tccAllocationMaskL
 32-bit "low" bitmask representing configuration provided list of TCCs for exclusive DMAN3 allocation.
Int heapInternal
 Memory Heap descriptor for dynamic allocation of DMAN3 objects that must be allocated in L1D Internal RAM.
Int heapExternal
 Memory Heap ID for dyn allocation of private DMAN3 data structures that can be allocated in external memory.
unsigned char numTccGroup [20]
 Array containing the number of TCCs that will be assigned to the algorithm groups for sharing.
unsigned short numPaRamGroup [20]
 Array containing the number of PaRams that will be assigned to the algorithm groups for sharing.
Bool idma3Internal
 Flag to indicate that the internal memory heap should be used for dynamic allocation of IDMA3 objects.
DMAN3_ScratchAllocFxn scratchAllocFxn
 Function for dynamic allocation of IDMA3 objects 'env' from shared scratch memory.
DMAN3_ScratchFreeFxn scratchFreeFxn
 Function for freeing IDMA3 objects 'env' from shared scratch memory.
Uns nullPaRamIndex
 Index of a reserved PaRam entry that will not be used for any DMA transfers. This PaRam will be used to set QCHMAP register to, when there is no activity on the corresponding QDMA channel.
Uns maxTCs
 The total number of Transfer Controllers available on the hardware (eg, 2 for DaVinci, 4 for Himalaya).
Uns * qdmaQueueMap
 Represents the mapping of the QDMA channels owned by DMAN3 to the event queue.
Uns * queueTCMap
 Represents the mapping of individual hardware Event queues to transfer controllers.
Uns * queuePri
 Represents the priority assigned to each of the Event Queues (and hence the Transfer Controllers).
Bool allowUnshared
 Flag indicating whether DMAN3 should allow algorithms to ask for more resources than configured into their scratch group.

Detailed Description

The module configuration structure for DMAN3 implementation. It is set at design time by the system integrator to ensure optimal sharing of DMA resources for the execution environment.

Remarks:
Typically, system integrators configure these settings using XDC config scripts. System integrators that use that method of configuration can ignore this structure definition. It's auto-generated during the config step by the XDC Tools.

Field Documentation

Uns* DMAN3_Params::qdmaPaRamBase

Physical base address of the PARAM0 in the EDMA3/QDMA hardware whose resources are being managed by DMAN3.

DMAN3_QDMA_PARAM_BASE

Uns DMAN3_Params::maxPaRamEntries

Total number of PARAM Table entries on the hardware (eg, for IVA2 this is 128, for Himalaya, this is 256).

DMAN3_MAX_PARAM_ENTRIES

Uns DMAN3_Params::paRamBaseIndex

Represents the first PARAM TABLE ENTRY NUMBER that is assigned by configuration for exclusive DMAN3 allocation.

Remarks:
Must be between zero and 255.

DMAN3_PARAM_BASE_INDEX

Uns DMAN3_Params::numPaRamEntries

Number of PARAM Table entries starting at DMAN3_PARAM_BASE_INDEX assigned by configuration for exclusive DMAN3 allocation.

DMAN3_NUM_CONTIGUOUS_PARAM_ENTRIES

Uns DMAN3_Params::maxQdmaChannels

The total number of Physical QDMA channels available on the hardware.

DMAN3_MAX_QDMA_CHANNELS

Uns DMAN3_Params::numQdmaChannels

The number of Physical QDMA channels that are assigned to DMAN3 via configuration.

DMAN3_NUM_QDMA_CHANNELS

Uns* DMAN3_Params::qdmaChannels

Array of size DMAN3_NUM_QDMA_CHANNELS that will contain the channel numbers of the Physical QDMA channels assigned to DMAN3 via configuration.

DMAN3_QDMA_CHANNELS[]

Uns DMAN3_Params::tccAllocationMaskH

32-bit "high" bitmask representing configuration provided list of TCCs for exclusive DMAN3 allocation.

Remarks:
For TCC's in the range 32-63, the High Mask (tccAllocationMaskH) is configured so that a '1' in bit position 'i' indicates the TCC '32 + i' is assigned to DMAN3.

DMAN3_TCC_FREEMASK_H

See also:
tccAllocationMaskL;
Uns DMAN3_Params::tccAllocationMaskL

32-bit "low" bitmask representing configuration provided list of TCCs for exclusive DMAN3 allocation.

Remarks:
For TCC's in the range 0-31, the Low Mask (tccAllocationMaskL) is configured so that a '1' in bit position 'i' indicates the TCC 'i' is assigned to DMAN3.

DMAN3_TCC_FREEMASK_L

See also:
tccAllocationMaskH;
Int DMAN3_Params::heapInternal

Memory Heap descriptor for dynamic allocation of DMAN3 objects that must be allocated in L1D Internal RAM.

Remarks:
A value of -1 indicates that the heap is NOT DEFINED.
If heapInternal is not defined then any IDMA3 protocol that requests IDMA3_INTERNAL type 'env' memory will fail.
See also:
heapExternal
Int DMAN3_Params::heapExternal

Memory Heap ID for dyn allocation of private DMAN3 data structures that can be allocated in external memory.

Remarks:
A value of -1 indicates that the heap is NOT DEFINED.
If heapExternal is not defined then DMAN3 attempts to use heapInternal. As a consequence at least one of them must be defined.
See also:
heapInternal
unsigned char DMAN3_Params::numTccGroup[20]

Array containing the number of TCCs that will be assigned to the algorithm groups for sharing.

Remarks:
Channels created with a given group ID will use TCCs allocated for that group ID, and may share them with other channels created with the same group ID. DMAN3_NUMTCC_GROUP
unsigned short DMAN3_Params::numPaRamGroup[20]

Array containing the number of PaRams that will be assigned to the algorithm groups for sharing.

Remarks:
Channels created with a given group ID will use PaRams allocated for that group ID, and may share them with other channels created with the same group ID. DMAN3_NUMPARAM_GROUP
Bool DMAN3_Params::idma3Internal

Flag to indicate that the internal memory heap should be used for dynamic allocation of IDMA3 objects.

Remarks:
A value of 0 means that IDMA3 objects will be allocated in the heap specified by heapExternal.
If the value of idma3Internal is non-zero, IDMA3 objects will be allocated in the heap specified by heapInternal.
DMAN3_ScratchAllocFxn DMAN3_Params::scratchAllocFxn

Function for dynamic allocation of IDMA3 objects 'env' from shared scratch memory.

Remarks:
If scratchAllocFxn is NULL then the 'env' will be allocated from persistent memory.
If scratchFreeFxn != NULL, then this function must not be NULL.
For example, to allocate 'env' in DSKT2 scratch memory, set scratchAllocFxn to DSKT2_allocScratch().
DMAN3_ScratchFreeFxn DMAN3_Params::scratchFreeFxn

Function for freeing IDMA3 objects 'env' from shared scratch memory.

Remarks:
If scratchAllocFxn is NULL then the 'env' will be freed from persistent memory.
If scratchAllocFxn != NULL, then this function must not be NULL.
For example, if 'env' is to be allocated in DSKT2 scratch memory, set scratchFreeFxn to DSKT2_freeScratch().
Uns DMAN3_Params::nullPaRamIndex

Index of a reserved PaRam entry that will not be used for any DMA transfers. This PaRam will be used to set QCHMAP register to, when there is no activity on the corresponding QDMA channel.

Uns DMAN3_Params::maxTCs

The total number of Transfer Controllers available on the hardware (eg, 2 for DaVinci, 4 for Himalaya).

Uns* DMAN3_Params::qdmaQueueMap

Represents the mapping of the QDMA channels owned by DMAN3 to the event queue.

Remarks:
For example, qdmaQueueMap[0] specifies queue number for qdmaChannel[0], etc.
Uns* DMAN3_Params::queueTCMap

Represents the mapping of individual hardware Event queues to transfer controllers.

Uns* DMAN3_Params::queuePri

Represents the priority assigned to each of the Event Queues (and hence the Transfer Controllers).

Bool DMAN3_Params::allowUnshared

Flag indicating whether DMAN3 should allow algorithms to ask for more resources than configured into their scratch group.

Remarks:
If this field is set to FALSE, the DMAN3 library will fail to grant DMA channels to an algorithm requesting more TCCs or PaRams then the number configured for its scratch group.
If this field is TRUE, and an algorithm requests more TCCs or PaRams than the number configured for its scratch group, DMAN3 will do either of the following:
  • If no algorithm is currently instantiated for the given scratch group, DMAN3 will bump up the number of TCCs and PaRams to the maximum of the number configured and that requested by the algorithm, for the scratch group. This will remain in effect until all algorithms for that scratch group are deleted.
  • If an algorithm has already been granted DMA channels for the given scratch group (so the number of TCCs and PaRams for that scratch group has already been determined by (1) above), and the number of TCCs or PaRams for the scratch group is insufficient for the algorithm currently requesting DMA channels, DMAN3 will allocate new TCCs and PaRams if available. These new TCCs and PaRams will not be shared by any other algorithm.
The documentation for this struct was generated from the following file:
Copyright 2010, Texas Instruments Incorporated