1    /* 
     2     * Copyright (c) 2011, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * 
    32     */
    33    
    34    
    35    /*!
    36     *  ======== DMAN3 ========
    37     *  EDMA3 QDMA resource manager.
    38     */
    39    @Template("./DMAN3.xdt")
    40    
    41    metaonly module DMAN3 {
    42    
    43        /* DMAN3 configuration settings for memory requirements */
    44        /*!
    45         *  ======== heapInternal ========
    46         *  Heap ID for dynamic allocation of DMAN3 objects.
    47         *
    48         *  This must be allocated in L1D Internal RAM.
    49         *
    50         *  This parameter is unused when DMAN3 is used in a Linux environment.
    51         *
    52         *  This parameter is set to `DMAN3_HEAP_INTERNAL`.
    53         */
    54        config String heapInternal = null;
    55    
    56        /*!
    57         *  ======== heapExternal ========
    58         *  Heap ID for dyn allocation of private DMAN3 data structures.
    59         *
    60         *  This parameter is unused when DMAN3 is used in a Linux environment.
    61         *
    62         *  This parameter is set to `DMAN3_HEAP_EXTERNAL`.
    63         */
    64        config String heapExternal = null;
    65    
    66        /*!
    67         *  ======== scratchAllocFxn ========
    68         *  Function for allocating IDMA3 channel object's "env" in scratch
    69         *  memory.
    70         */
    71        config String scratchAllocFxn = null;
    72    
    73        /*!
    74         *  ======== scratchFreeFxn ========
    75         *  Function for freeing IDMA3 channel object's "env" that was allocated
    76         *  in scratch memory.
    77         */
    78        config String scratchFreeFxn = null;
    79    
    80        /*!
    81         *  ======== idma3Internal ========
    82         *  Use the internal memory heap for dynamic allocation of IDMA3 objects.
    83         *
    84         *  A value of `false` means that IDMA3 objects will be allocated
    85         *  in the heap specified by {@link #heapExternal}. If the
    86         *  value is `true`, IDMA3 objects will be
    87         *  allocated in the heap specified by {@link #heapInternal}.
    88         */
    89        config bool idma3Internal = true;
    90    
    91        /*!
    92         *  ======== cpu ========
    93         *  Use the non-EDMA3, CPU version of DMAN3.
    94         */
    95        config bool cpu = false;
    96    
    97        /*!
    98         *  ======= useExternalRM =======
    99         *  Boolean flag indicating if the EDMA3 Low Level
   100         *  Resource Manager should be used to manage EDMA3
   101         *  resources. If this flag is set to true, the SOC
   102         *  specific settings are not required to be set in
   103         *  this module. The ti.sdo.fc.edma3.Settings module
   104         *  should be set up correctly
   105         */
   106        config bool useExternalRM = false;
   107    
   108        /*!
   109         *  ======== numQdmaChannels ========
   110         *  The number of Physical QDMA channels that are assigned to
   111         *  DMAN3 via configuration. These channels will be granted either
   112         *  as scratch or persistently as part of IDMA3 handles.
   113         *
   114         *  This parameter is set to `DMAN3_NUM_QDMA_CHANNELS`.
   115         */
   116        config UInt numQdmaChannels = 4;
   117    
   118        /* If DMAN3.useExternalRM is set to true, the SOC specific settings below
   119           are ignored.
   120        */
   121        /* SOC specific settings for EDMA3 */
   122    
   123        /*!
   124         *  ======== qdmaPaRamBase ========
   125         *  Physical base address of the PARAM0 in the EDMA3/QDMA
   126         *  hardware whose resources are being managed by DMAN3.
   127         *
   128         *  This parameter is set to `DMAN3_QDMA_PARAM_BASE`.
   129         */
   130        config Ptr  qdmaPaRamBase =  0x01C04000;
   131    
   132        /*!
   133         *  ======== maxPaRamEntries ========
   134         *  Total number of PARAM Table entries on the target hardware.
   135         *  (eg, for IVA2, Davinci this is 128, for Himalaya, this is 256).
   136         *
   137         *  This parameter is set to `DMAN3_MAX_PARAM_ENTRIES`.
   138         */
   139        config UInt maxPaRamEntries = 128;
   140    
   141        /*!
   142         *  ======== maxQdmaChannels ========
   143         *  The total number of Physical QDMA channels available on the
   144         *  target hardware (eg, 8 for DaVinci, 4 for IVA2).
   145         *
   146         *  This parameter is set to `DMAN3_MAX_QDMA_CHANNELS`.
   147         */
   148        config UInt maxQdmaChannels = 8;
   149    
   150       /*!
   151        *  ======= maxTCs ========
   152        *  Maximum number of transfer controllers on this SOC
   153        */
   154        config UInt maxTCs = 8;
   155    
   156        /* DMAN3 resource configuration settings */
   157        /* If DMAN3.useExternalRM is set to true, the resource specific settings
   158           below are ignored.
   159           Instead setup the ti.sdo.fc.edma3.Settings module with the EDMA3
   160           that you would like to make available to this region */
   161    
   162        /*!
   163         *  ======== paRamBaseIndex ========
   164         *  (0 > value > 255) represents the first PARAM TABLE ENTRY NUMBER
   165         *  that is assigned by configuration for exclusive DMAN3 allocation.
   166         *
   167         *  Typically, addresses (PaRam sets) between 0 and 63 are reserved for use
   168         *  by drivers that need EDMA/chaining capabilities.
   169         *
   170         *  Additionally, on some multi-core devices (e.g. DM644x), PaRams are
   171         *  shared between the different cores (e.g. ARM and C64+).  In these
   172         *  cases, an executable will be configured for each core, and each
   173         *  executable should configure only the DMAN3 resources which will be used
   174         *  on that core.  E.g., on DM644x, the C64+ executable should
   175         *  be configured to avoid using what the ARM uses.  Note that on
   176         *  OMAP2430, the ARM doesn't have access to EDMA so all PaRam sets
   177         *  are available for the C64+ device.
   178         *
   179         *  This parameter is set to `DMAN3_PARAM_BASE_INDEX`.
   180         */
   181        config UInt paRamBaseIndex =  96;
   182    
   183        /*!
   184         *  ======== numPaRamEntries ========
   185         *  Number of PARAM Table entries starting at DMAN3_PARAM_BASE_INDEX
   186         *  assigned by configuration for exclusive DMAN3 allocation.
   187         *
   188         *  This parameter is set to `DMAN3_NUM_CONTIGUOUS_PARAM_ENTRIES`.
   189         */
   190        config UInt numPaRamEntries = 32;
   191    
   192        /*!
   193         *  ======== nullPaRamIndex ========
   194         *  Index of PaRam to be reserved as a "null" PaRam. This index will be
   195         *  used to set QCHMAP when the corresponding QDMA channel is not active.
   196         *  The value of nullPaRamIndex should be outside of the range of
   197         *  PaRam indices alloted to DMAN3, i.e., nullPaRamIndex should be less
   198         *  than paRamBaseIndex, or greater than paRamBaseIndex + numPaRamEntries.
   199         *  If PaRam registers are shared between two processors (eg, an Arm
   200         *  and a DSP), make sure the nullPaRamIndex is not used by the other
   201         *  processor.
   202         *
   203         *  This parameter is set to `DMAN3_NULLPARAMINDEX`.
   204         */
   205        config UInt nullPaRamIndex = 0;
   206    
   207        /*!
   208         *  ======== qdmaChannels ========
   209         *  Array containing list of physical QDMA channels assigned to DMAN3.
   210         *
   211         *  This array is of size `DMAN3_NUM_QDMA_CHANNELS`
   212         *  (configured by {@link #numQdmaChannels}).
   213         *
   214         *  This parameter is set to `DMAN3_QDMA_CHANNELS[]`.
   215         *
   216         *  @see numQdmaChannels
   217         */
   218        config UInt qdmaChannels[] = [0, 1, 2, 3];
   219    
   220        /*!
   221         *  ======== tccAllocationMaskH ========
   222         *  32-bit bitmask representing configuration provided list of TCCs
   223         *  for exclusive DMAN3 allocation.
   224         *
   225         *  For example, for TCC's in the range 0-31 the Low Mask
   226         *  (tccAllocationMaskL) is configured so that a '1' in bit position 'i'
   227         *  indicates the TCC 'i' is assigned to DMAN3.
   228         *
   229         *  This parameter is set to `DMAN3_TCC_FREEMASK_H`.
   230         */
   231        config UInt tccAllocationMaskH = 0xffffffff;
   232    
   233        /*!
   234         *  ======== tccAllocationMaskL ========
   235         *  32-bit bitmask representing configuration provided list of TCCs
   236         *  for exclusive DMAN3 allocation.
   237         *
   238         *  For example, for TCC's in the range 0-31 the Low Mask
   239         *  (tccAllocationMaskL) is configured so that a '1' in bit position 'i'
   240         *  indicates the TCC 'i' is assigned to DMAN3.
   241         *
   242         *  This parameter is set to `DMAN3_TCC_FREEMASK_L`.
   243         */
   244        config UInt tccAllocationMaskL = 0x00000000;
   245    
   246        /*!
   247         *  ======= qdmaQueueMap ========
   248         *  Array contaning the mapping from QDMA Channels to Event Queues
   249         *
   250         *  Indicates mapping of all "qdmaChannels" defined above to
   251         *  particular Event Queue.  For example, `channelQueueMap[0]`
   252         *  specifies queue number for `qdmaChannel[0]`, etc.
   253         *
   254         *  Defaults map all qdmaChannels to Queue# 1
   255         */
   256        config UInt qdmaQueueMap[] = [1,1,1,1,1,1,1,1];
   257    
   258        /*!
   259         *  ======= queueTCMap ========
   260         * Array contaning the mapping from Event Queues to Transfer Controllers
   261         *
   262         * Indicates mapping of individual hardware Event Queues to the Transfer
   263         * Controllers.
   264         */
   265        config UInt queueTCMap[] = [0, 1, 2, 3, 4, 5, 6, 7];
   266    
   267        /*!
   268         *  ======= queuePri ========
   269         * Array contaning priorities of the event queues
   270         *
   271         * Indicates the priority accorded to each physical event queue.
   272         */
   273        config UInt queuePri[] = [3, 7, 0, 0, 0, 0, 0, 0];
   274    
   275        /* These const values must match those in dman3.h */
   276    
   277        const Int MAXGROUPS = 20;  /*! Maximum number of groups for sharing
   278                                     TCCs and parameter RAM. */
   279    
   280        /* DMAN3 configuration settings  for scratch groups */
   281    
   282        /*!
   283         *  ======== numTccGroup ========
   284         *  Arrays containing the number of TCC that will be assigned to groups for
   285         *  sharing
   286         *
   287         *  Channels created with a given group ID will use TCCs and PaRams
   288         *  allocated for that group ID, and may share them with other channels
   289         *  created with the same group ID.
   290         *
   291         *  This parameter is set to `DMAN3_NUMTCC_GROUP`.
   292         */
   293        config Int numTccGroup[MAXGROUPS] = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0, 0, 0,
   294                0, 0, 0, 0, 0, 0, 0,];
   295    
   296        /*!
   297         *  ======== numPaRamGroup ========
   298         *  Arrays containing the number of PaRam entries that will be assigned to
   299         * groups for sharing.
   300         *
   301         *  Channels created with a given group ID will use TCCs and PaRams
   302         *  allocated for that group ID, and may share them with other channels
   303         *  created with the same group ID.
   304         *
   305         *  This parameter is set to `DMAN3_NUMPARAM_GROUP`.
   306         */
   307        config Int numPaRamGroup[MAXGROUPS]= [0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0, 0, 0,
   308                0, 0, 0, 0, 0, 0, 0,] ;
   309    
   310        /*
   311         * TODO:  These "Strings" should be Ints... how do we get a handle to
   312         * the BIOS objects in javascript-land?
   313         */
   314    
   315        /*!
   316         *  ======== multiProcess ========
   317         *  Enable multi-process support in the DMAN3 library.
   318         *  @_nodoc
   319         */
   320        config bool multiProcess = true;
   321    
   322        /*!
   323         *  ======== ipcKeyBase ========
   324         *  Linux only. Base value of keys of Linux IPC objects used by
   325         *  DMAN3. The IPC objects created by DMAN3 will use keys starting at this
   326         *  value, and incrementing with each new object. There are currently
   327         *  three IPC objects, so keys in the range of ipcKeyBase to ipcKeyBase + 2
   328         *  will be reserved for DMAN3. The default value of ipcKeyBase is
   329         *  ascii code for "NAMD".
   330         *
   331         *  WARNING: This value should only be changed if it conflicts with
   332         *  another IPC key in the system that cannot be changed. If this value
   333         *  is changed, all programs using DMAN3 that will be run simultaneously
   334         *  must have the ipcKeyBase configured to the new value.
   335         *  @_nodoc
   336         */
   337        config UInt ipcKeyBase = 0x4e414d44;
   338    
   339        /*!
   340         *  ======== allowUnshared ========
   341         *  Allow DMAN3-related resources to be granted to an algorithm, even
   342         *  if there are not enough resources configured into the shared
   343         *  groupId which the algorithm is a member of.
   344         *
   345         *  If this property is set to `false`, the DMAN3 library will fail
   346         *  to grant DMA channels to an algorithm requesting more TCCs or
   347         *  PaRams then the number configured for its scratch group.
   348         *
   349         *  If this property is `true`, and an algorithm requests more TCCs or
   350         *  PaRams than the number configured for its scratch group, DMAN3 will
   351         *  do either of the following:
   352         *  @p(nlist)
   353         *     - If no algorithm is currently instantiated for the given scratch
   354         *       group, DMAN3 will bump up the number of TCCs and PaRams to the
   355         *       maximum of the number configured and that requested by the
   356         *       algorithm, for the scratch group. This will remain in effect
   357         *       until all algorithms for that scratch group are deleted.
   358         *     - If an algorithm has already been granted DMA channels for the
   359         *       given scratch group (so the number of TCCs and PaRams for that
   360         *       scratch group has already been determined by (1) above), and the
   361         *       number of TCCs or PaRams for the scratch group is insufficient for
   362         *       the algorithm currently requesting DMA channels, DMAN3 will
   363         *       allocate new TCCs and PaRams if available. These new TCCs and
   364         *       PaRams will not be shared by any other algorithm.
   365         */
   366        config bool allowUnshared = true;
   367    
   368    }
   369    /*
   370     *  @(#) ti.sdo.fc.dman3; 1, 0, 4,403; 3-1-2011 18:56:43; /db/atree/library/trees/fc/fc-n29x/src/ xlibrary
   371    
   372     */
   373