Texas Instruments

Table of Contents

TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 16.12.0

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 127
Hwi_restore() 9
Hwi_disable() 13
Hwi dispatcher prolog 107
Hwi dispatcher epilog 234
Hwi dispatcher 337
Hardware Interrupt to Blocked Task 555
Hardware Interrupt to Software Interrupt 377
Swi_enable() 81
Swi_disable() 10
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 99
Post Software Interrupt with Context Switch 193
Create a New Task without Context Switch 2004
Set a Task Priority without a Context Switch 174
Task_yield() 215
Post Semaphore No Waiting Task 53
Post Semaphore No Task Switch 198
Post Semaphore with Task Switch 269
Pend on Semaphore No Context Switch 83
Pend on Semaphore with Task Switch 291
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 4069
POSIX Set a Task Priority without a Context Switch 241
POSIX Post Semaphore No Waiting Task 65
POSIX Post Semaphore No Task Switch 216
POSIX Post Semaphore with Task Switch 283
POSIX Pend on Semaphore No Context Switch 94
POSIX Pend on Semaphore with Task Switch 302

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.