The Cortex M3's Nested Vectored Interrupt Controller (NVIC)
supports 256 interrupts/exceptions.
SYS/BIOS Interrupt IDs or interrupt numbers correspond
to an interrupt's position in the interrupt vector table.
ID 0 corresponds to vector 0 which is used by the NVIC
to hold the initial (reset) stack pointer value.
IDs 1-14 are hardwired to exceptions.
ID 15 is the SysTick timer interrupt.
ID's 16-255 are mapped to the NVIC's user interrupts 0-239
which are tied to platform specific interrupt sources.
Due to the M3's native automatic stacking of saved-by-caller C
context on the way to an ISR, zero latency interrupt handlers
are implemented using regular C functions (ie no 'interrupt'
keyword is required).
enum Hwi_MaskingOption |
|
Shorthand interrupt masking options
typedef enum Hwi_MaskingOption {
Hwi_MaskingOption_NONE,
// No interrupts are disabled
Hwi_MaskingOption_ALL,
// All interrupts are disabled
Hwi_MaskingOption_SELF,
// Only this interrupt is disabled
Hwi_MaskingOption_BITMASK,
// User supplies IER masks
Hwi_MaskingOption_LOWER
// All current and lower priority
interrupts are disabled. Only a few
targets/devices truly support this
masking option. For those that don't,
this setting is treated the same as
MaskingOption_SELF
} Hwi_MaskingOption;
typedef Hwi_ExceptionHookFuncPtr |
|
Exception hook function type definition
typedef Hwi_FuncPtr |
|
Hwi create function type definition
typedef Void (*Hwi_FuncPtr)(UArg);
typedef Hwi_Irp |
|
Interrupt Return Pointer.
This is the address of the interrupted instruction
typedef Hwi_VectorFuncPtr |
|
Hwi vector function type definition
typedef Void (*Hwi_VectorFuncPtr)(Void);
struct Hwi_CCR |
|
NVIC Configuration Control Register (CCR)
typedef struct Hwi_CCR {
Bits8 STKALIGN;
// Auto stack alignment in exception
Bits8 BFHFNMIGN;
// All faults ignore BUS Faults
Bits8 DIV_0_TRP;
// Trap on divige be zero
Bits8 UNALIGN_TRP;
// Trap on all unaligned accesses
Bits8 USERSETMPEND;
// Allow user to trigger interrupts
Bits8 NONEBASETHRDENA;
// Allow entering thread mode anytime
} Hwi_CCR;
struct Hwi_ExcContext |
|
Exception Context - Register contents at the time of an exception
typedef struct Hwi_ExcContext {
Ptr threadHandle;
Ptr threadStack;
SizeT threadStackSize;
Ptr r0;
Ptr r1;
Ptr r2;
Ptr r3;
Ptr r4;
Ptr r5;
Ptr r6;
Ptr r7;
Ptr r8;
Ptr r9;
Ptr r10;
Ptr r11;
Ptr r12;
Ptr sp;
Ptr lr;
Ptr pc;
Ptr psr;
Ptr ICSR;
Ptr MMFSR;
Ptr BFSR;
Ptr UFSR;
Ptr HFSR;
Ptr DFSR;
Ptr MMAR;
Ptr BFAR;
Ptr AFSR;
} Hwi_ExcContext;
struct Hwi_HookSet |
|
Hwi hook set type definition
typedef struct Hwi_HookSet {
Void (*registerFxn)(Int);
} Hwi_HookSet;
DETAILS
The functions that make up a hookSet have certain restrictions. They
cannot call any Hwi instance functions other than Hwi_getHookContext()
and Hwi_setHookContext(). For all practical purposes, they should treat
the Hwi_Handle passed to these functions as an opaque handle.
struct Hwi_NVIC |
|
Nested Vectored Interrupt Controller
typedef struct Hwi_NVIC {
UInt32 RES_00;
// 0xE000E000 reserved
UInt32 ICTR;
// 0xE000E004 Interrupt Control Type
UInt32 RES_08;
// 0xE000E008 reserved
UInt32 RES_0C;
// 0xE000E00C reserved
UInt32 STCSR;
// 0xE000E010 SysTick Control & Status Register
UInt32 STRVR;
// 0xE000E014 SysTick Reload Value Register
UInt32 STCVR;
// 0xE000E018 SysTick Current Value Register
UInt32 STCALIB;
// 0xE000E01C SysTick Calibration Value Register
UInt32 RES_20[56];
// 0xE000E020-0xE000E0FC reserved
UInt32 ISER[8];
// 0xE000E100-0xE000E11C Interrupt Set Enable Registers
UInt32 RES_120[24];
// 0xE000E120-0xE000E17C reserved
UInt32 ICER[8];
// 0xE000E180-0xE000E19C Interrupt Clear Enable Registers
UInt32 RES_1A0[24];
// 0xE000E1A0-0xE000E1FC reserved
UInt32 ISPR[8];
// 0xE000E200-0xE000E21C Interrupt Set Pending Registers
UInt32 RES_220[24];
// 0xE000E220-0xE000E7C reserved
UInt32 ICPR[8];
// 0xE000E280-0xE000E29C Interrupt Clear Pending Registers
UInt32 RES_2A0[24];
// 0xE000E2A0-0xE000E2FC reserved
UInt32 IABR[8];
// 0xE000E300-0xE000E31C Interrupt Active Bit Registers
UInt32 RES_320[56];
// 0xE000E320-0xE000E3FC reserved
UInt8 IPR[240];
// 0xE000E400-0xE000E4EF Interrupt Priority Registers
UInt32 RES_4F0[516];
// 0xE000E4F0-0xE000ECFC reserved
UInt32 CPUIDBR;
// 0xE000ED00 CPUID Base Register
UInt32 ICSR;
// 0xE000ED04 Interrupt Control State Register
UInt32 VTOR;
// 0xE000ED08 Vector Table Offset Register
UInt32 AIRCR;
// 0xE000ED0C Application Interrupt/Reset Control Register
UInt32 SCR;
// 0xE000ED10 System Control Register
UInt32 CCR;
// 0xE000ED14 Configuration Control Register
UInt8 SHPR[12];
// 0xE000ED18 System Handlers 4-15 Priority Registers
UInt32 SHCSR;
// 0xE000ED24 System Handler Control & State Register
UInt8 MMFSR;
// 0xE000ED28 Memory Manage Fault Status Register
UInt8 BFSR;
// 0xE000ED29 Bus Fault Status Register
UInt16 UFSR;
// 0xE000ED2A Usage Fault Status Register
UInt32 HFSR;
// 0xE000ED2C Hard Fault Status Register
UInt32 DFSR;
// 0xE000ED30 Debug Fault Status Register
UInt32 MMAR;
// 0xE000ED34 Memory Manager Address Register
UInt32 BFAR;
// 0xE000ED38 Bus Fault Address Register
UInt32 AFSR;
// 0xE000ED3C Auxiliary Fault Status Register
UInt32 PFR0;
// 0xE000ED40 Processor Feature Register
UInt32 PFR1;
// 0xE000ED44 Processor Feature Register
UInt32 DFR0;
// 0xE000ED48 Debug Feature Register
UInt32 AFR0;
// 0xE000ED4C Auxiliary Feature Register
UInt32 MMFR0;
// 0xE000ED50 Memory Model Fault Register0
UInt32 MMFR1;
// 0xE000ED54 Memory Model Fault Register1
UInt32 MMFR2;
// 0xE000ED58 Memory Model Fault Register2
UInt32 MMFR3;
// 0xE000ED5C Memory Model Fault Register3
UInt32 ISAR0;
// 0xE000ED60 ISA Feature Register0
UInt32 ISAR1;
// 0xE000ED64 ISA Feature Register1
UInt32 ISAR2;
// 0xE000ED68 ISA Feature Register2
UInt32 ISAR3;
// 0xE000ED6C ISA Feature Register3
UInt32 ISAR4;
// 0xE000ED70 ISA Feature Register4
UInt32 RES_D74[99];
// 0xE000ED74-0xE000EEFC reserved
UInt32 STI;
// 0xE000EF00 Software Trigger Interrupt Register
UInt32 PID4;
// 0xE000EFD0 Peripheral ID Register4
UInt32 PID5;
// 0xE000EFD4 Peripheral ID Register5
UInt32 PID6;
// 0xE000EFD8 Peripheral ID Register6
UInt32 PID7;
// 0xE000EFDC Peripheral ID Register7
UInt32 PID0;
// 0xE000EFE0 Peripheral ID Register0
UInt32 PID1;
// 0xE000EFE4 Peripheral ID Register1
UInt32 PID2;
// 0xE000EFE8 Peripheral ID Register2
UInt32 PID3;
// 0xE000EFEC Peripheral ID Register3
UInt32 CID0;
// 0xE000EFF0 Component ID Register0
UInt32 CID1;
// 0xE000EFF4 Component ID Register1
UInt32 CID2;
// 0xE000EFF8 Component ID Register2
UInt32 CID3;
// 0xE000EFFC Component ID Register3
} Hwi_NVIC;
config Hwi_NUM_INTERRUPTS // module-wide |
|
The Cortex M3 NVIC supports up to 256 interrupts/exceptions
extern const Int Hwi_NUM_INTERRUPTS;
DETAILS
The actual number supported is device specific and provided by
the catalog device specification.
config Hwi_NUM_PRIORITIES // module-wide |
|
The Cortex M3 NVIC supports up to 256 interrupt priorities
extern const Int Hwi_NUM_PRIORITIES;
DETAILS
The actual number supported is device specific and provided by
the catalog device specification.
config Hwi_A_unsupportedMaskingOption // module-wide |
|
Assert when bad maskSetting parameter provided
extern const Assert_Id Hwi_A_unsupportedMaskingOption;
config Hwi_E_NMI // module-wide |
|
Error raised when NMI exception occurs
config Hwi_E_alreadyDefined // module-wide |
|
Error raised when Hwi is already defined
extern const Error_Id Hwi_E_alreadyDefined;
config Hwi_E_busFault // module-wide |
|
Error raised when bus fault exception occurs
config Hwi_E_debugMon // module-wide |
|
Error raised when debugMon exception occurs
config Hwi_E_exception // module-wide |
|
Error raised when an exception occurs
config Hwi_E_hardFault // module-wide |
|
Error raised when hard fault exception occurs
config Hwi_E_memFault // module-wide |
|
Error raised when memory fault exception occurs
config Hwi_E_noIsr // module-wide |
|
Error raised when an uninitialized interrupt occurs
config Hwi_E_reserved // module-wide |
|
Error raised when reserved exception occurs
config Hwi_E_svCall // module-wide |
|
Error raised when svCall exception occurs
config Hwi_E_usageFault // module-wide |
|
Error raised when usage fault exception occurs
config Hwi_LD_end // module-wide |
|
Issued just after return from Hwi function (with interrupts disabled)
config Hwi_LM_begin // module-wide |
|
Issued just prior to Hwi function invocation (with interrupts disabled)
config Hwi_disablePriority // module-wide |
|
The priority that BASEPRI is set to by Hwi_disable()
extern const UInt Hwi_disablePriority;
DETAILS
All interrupts configured with equal or less priority (equal or
higher number) than disablePriority are disabled by Hwi_disable.
Interrupts configured with higher priority (smaller number) than
disablePriority are non-maskable (ie zero-latency).
The default setting is the second highest interrupt priority
defined for the device. This results in priority 0 (and all
other values in the same priority group) being
the non-maskable interrupt priority. All other priorities
are disabled with Hwi_disable().
config Hwi_dispatcherAutoNestingSupport // module-wide |
|
Include interrupt nesting logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherAutoNestingSupport;
DETAILS
Default is true.
This option provides the user with the ability to optimize
interrupt dispatcher performance when support for interrupt
nesting is not required.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that manipulates interrupt mask
registers and enables and disables interrupts before and
after invoking the user's Hwi function.
Set this parameter to false if you don't need interrupts
enabled during the execution of your Hwi functions.
config Hwi_dispatcherIrpTrackingSupport // module-wide |
|
Controls whether the
dispatcher retains the interrupted thread's return address
extern const Bool Hwi_dispatcherIrpTrackingSupport;
DETAILS
This option is enabled by default.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that keeps track of the interrupt's
return address and provide a small savings in interrupt latency.
The application can get an interrupt's most recent return
address using the
getIrp API.
config Hwi_dispatcherSwiSupport // module-wide |
|
Include Swi scheduling logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherSwiSupport;
DETAILS
Default is inherited from
BIOS.swiEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that Swis
will not be posted from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Swi scheduler
prior to returning from an interrupt.
config Hwi_dispatcherTaskSupport // module-wide |
|
Include Task scheduling logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherTaskSupport;
DETAILS
Default is inherited from
BIOS.taskEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that no
Task scheduling APIs (ie
Semaphore_post()) will be executed from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Task scheduler
prior to returning from an interrupt.
config Hwi_excHookFunc // module-wide |
|
User Exception hook function
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
config Hwi_priGroup // module-wide |
|
The PRIGROUP setting. Default is 0
extern const UInt Hwi_priGroup;
DETAILS
This value will be written to the PRIGROUP field
within the NVIC's Application Interrupt and Reset Control
Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
values are interpreted by the hardware.
Valid settings are 0-7.
The default setting of 0 causes bits 7-1 of an interrupt's
priority value to be used to as a pre-emption priority, and bit 0
is used to determine which of two simultaneous interrupts with
the same pre-emption priority will be serviced first.
Hwi_clearInterrupt() // module-wide |
|
Clear a specific interrupt
Void Hwi_clearInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to clear
DETAILS
Clears a specific interrupt's pending status.
The implementation is family-specific.
Hwi_disable() // module-wide |
|
Globally disable interrupts
RETURNS
opaque key for use by Hwi_restore()
DETAILS
Hwi_disable globally disables hardware interrupts and returns an
opaque key indicating whether interrupts were globally enabled or
disabled on entry to Hwi_disable().
The actual value of the key is target/device specific and is meant
to be passed to Hwi_restore().
Call Hwi_disable before a portion of a function that needs
to run without interruption. When critical processing is complete, call
Hwi_restore or Hwi_enable to reenable hardware interrupts.
Servicing of interrupts that occur while interrupts are disabled is
postponed until interrupts are reenabled. However, if the same type
of interrupt occurs several times while interrupts are disabled,
the interrupt's function is executed only once when interrupts are
reenabled.
A context switch can occur when calling Hwi_enable or Hwi_restore if
an enabled interrupt occurred while interrupts are disabled.
Hwi_disable may be called from main(). However, since Hwi interrupts
are already disabled in main(), such a call has no effect.
CONSTRAINTS
If a Task switching API such as
Semaphore_pend(),
Semaphore_post(),
Task_sleep(), or
Task_yield()
is invoked which results in a context switch while
interrupts are disabled, an embedded call to
Hwi_enable occurs
on the way to the new thread context which unconditionally re-enables
interrupts. Interrupts will remain enabled until a subsequent
Hwi_disable
invocation.
Swis always run with interrupts enabled.
See
Swi_post() for a discussion Swis and
interrupts.
Hwi_disableInterrupt() // module-wide |
|
Disable a specific interrupt
UInt Hwi_disableInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to disable
RETURNS
key to restore previous enable/disable state
DETAILS
Disable a specific interrupt identified by an interrupt number.
Hwi_enable() // module-wide |
|
Globally enable interrupts
RETURNS
opaque key for use by Hwi_restore()
DETAILS
Hwi_enable globally enables hardware interrupts and returns an
opaque key indicating whether interrupts were globally enabled or
disabled on entry to Hwi_enable().
The actual value of the key is target/device specific and is meant
to be passed to Hwi_restore().
This function is
called as part of SYS/BIOS Startup_POST_APP_MAIN phase.
Hardware interrupts are enabled unless a call to Hwi_disable disables
them.
Servicing of interrupts that occur while interrupts are disabled is
postponed until interrupts are reenabled. However, if the same type
of interrupt occurs several times while interrupts are disabled,
the interrupt's function is executed only once when interrupts are
reenabled.
A context switch can occur when calling Hwi_enable or Hwi_restore if
an enabled interrupt occurred while interrupts are disabled.
Any call to Hwi_enable enables interrupts, even if Hwi_disable has
been called several times.
Hwi_enable must not be called from main().
Hwi_enableInterrupt() // module-wide |
|
Enable a specific interrupt
UInt Hwi_enableInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to enable
RETURNS
key to restore previous enable/disable state
DETAILS
Enables a specific interrupt identified by an interrupt number.
Hwi_excSetBuffers() // module-wide |
|
Set the exception context and stack buffer pointers
Void Hwi_excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
ARGUMENTS
excContextBuffer
Address to place ExcContext
excStackBuffer
Address to place ExcStack
Hwi_getHandle() // module-wide |
|
Returns Hwi_handle associated with intNum
ARGUMENTS
intNum
interrupt number
Hwi_restore() // module-wide |
|
Globally restore interrupts
Void Hwi_restore(UInt key);
ARGUMENTS
key
enable/disable state to restore
DETAILS
Hwi_restore globally restores interrupts to the state determined
by the key argument provided by a previous invocation of Hwi_disable.
A context switch may occur when calling Hwi_restore if Hwi_restore
reenables interrupts and another Hwi occurred while interrupts were
disabled.
Hwi_restore may be called from main(). However, since Hwi_enable
cannot be called from main(), interrupts are always disabled in
main(), and a call to Hwi_restore has no effect.
Hwi_restoreInterrupt() // module-wide |
|
Restore a specific interrupt's enabled/disabled state
Void Hwi_restoreInterrupt(UInt intNum, UInt key);
ARGUMENTS
intNum
interrupt number to restore
key
key returned from enableInt or disableInt
DETAILS
Restores a specific interrupt identified by an interrupt number.
restoreInterrupt is generally used to restore an interrupt to its state
before
disableInterrupt or
enableInterrupt was
invoked
Hwi_setPriority() // module-wide |
|
Set an interrupt's relative priority
Void Hwi_setPriority(UInt intNum, UInt priority);
ARGUMENTS
intNum
ID of interrupt
priority
priority
DETAILS
Valid priorities are 0 - 255. 0 is highest priority.
Hwi_startup() // module-wide |
|
Initially enable interrupts
DETAILS
Called within BIOS_start
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Hwi_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Hwi_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Hwi_Module_getMask();
// Returns the diagnostics mask for this module
Void Hwi_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
Instance Object Types |
|
typedef struct Hwi_Object Hwi_Object;
// Opaque internal representation of an instance object
// Client reference to an instance object
typedef struct Hwi_Struct Hwi_Struct;
// Opaque client structure large enough to hold an instance object
// Convert this instance structure pointer into an instance handle
// Convert this instance handle into an instance structure pointer
Instance Config Parameters |
|
typedef struct Hwi_Params {
// Instance config-params structure
// Common per-instance configs
UArg arg;
// ISR function argument. Default is 0
Bool enableInt;
// Enable this interrupt now? Default is true
Int eventId;
// Interrupt event ID (Interrupt Selection Number)
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored
// The interrupt controller is designed for priority based interrupts
Int priority;
// Interrupt priority.
Valid priorities are 0 - 255. 0 is the highest priority.
The default is 255 which is the lowest priority interrupt
} Hwi_Params;
// Initialize this config-params structure with supplier-specified defaults before instance creation
config Hwi_arg // instance |
|
ISR function argument. Default is 0
config Hwi_enableInt // instance |
|
Enable this interrupt now? Default is true
config Hwi_eventId // instance |
|
Interrupt event ID (Interrupt Selection Number)
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored
config Hwi_maskSetting // instance |
|
The interrupt controller is designed for priority based interrupts
config Hwi_priority // instance |
|
Interrupt priority.
Valid priorities are 0 - 255. 0 is the highest priority.
The default is 255 which is the lowest priority interrupt
Instance Creation |
|
// Allocate and initialize a new instance object and return its handle
// Initialize a new instance object inside the provided structure
ARGUMENTS
intNum
interrupt number
hwiFxn
pointer to ISR function
params
per-instance config params, or NULL to select default values (target-domain only)
eb
active error-handling block, or NULL to select default policy (target-domain only)
DETAILS
A Hwi dispatcher table entry is created and filled with the
function specified by the fxn parameter and the attributes
specified by the params parameter.
If params is NULL, the Hwi's dispatcher properties are assigned a
default set of values. Otherwise, the following properties
are specified by a structure of type Hwi_Params.
- The arg element is a generic argument that is passed to the plugged
function as its only parameter. The default value is 0.
- The enableInt element determines whether the interrupt should be
enabled in the IER by create.
- The maskSetting element defines the dispatcherAutoNestingSupport
behavior of the interrupt.
Hwi_create returns a pointer to the created Hwi object.
Instance Deletion |
|
// Finalize and free this previously allocated instance object, setting the referenced handle to NULL
// Finalize the instance object inside the provided structure
Hwi_getFunc() // instance |
|
Get Hwi function and arg
ARGUMENTS
handle
handle of a previously-created Hwi instance object
arg
pointer for returning hwi's ISR function argument
RETURNS
hwi's ISR function
Hwi_getHookContext() // instance |
|
Get hook instance's context for a Hwi
Ptr Hwi_getHookContext(
Hwi_Handle handle,
Int id);
ARGUMENTS
handle
handle of a previously-created Hwi instance object
RETURNS
hook instance's context for hwi
Hwi_getIrp() // instance |
|
Get address of interrupted instruction
ARGUMENTS
handle
handle of a previously-created Hwi instance object
RETURNS
most current IRP of a Hwi
Hwi_reconfig() // instance |
|
Reconfigure a dispatched interrupt
ARGUMENTS
handle
handle of a previously-created Hwi instance object
Hwi_setFunc() // instance |
|
Overwrite Hwi function and arg
ARGUMENTS
handle
handle of a previously-created Hwi instance object
fxn
pointer to ISR function
arg
argument to ISR function
DETAILS
Replaces a Hwi object's hwiFxn function originally
provided in
create.
Hwi_setHookContext() // instance |
|
Set hook instance's context for a Hwi
Void Hwi_setHookContext(
Hwi_Handle handle,
Int id,
Ptr hookContext);
ARGUMENTS
handle
handle of a previously-created Hwi instance object
id
hook instance's ID
hookContext
value to write to context
Instance Convertors |
|
// unconditionally move one level up the inheritance hierarchy
// conditionally move one level down the inheritance hierarchy; NULL upon failure
Instance Built-Ins |
|
Int Hwi_Object_count();
// The number of statically-created instance objects
// The handle of the i-th statically-created instance object (array == NULL)
// The handle of the first dynamically-created instance object, or NULL
// The handle of the next dynamically-created instance object, or NULL
// The heap used to allocate dynamically-created instance objects
// The label associated with this instance object
// The name of this instance object
enum Hwi.MaskingOption |
|
Shorthand interrupt masking options
XDCscript usage |
meta-domain |
values of type Hwi.MaskingOption
const Hwi.MaskingOption_NONE;
// No interrupts are disabled
const Hwi.MaskingOption_ALL;
// All interrupts are disabled
const Hwi.MaskingOption_SELF;
// Only this interrupt is disabled
const Hwi.MaskingOption_BITMASK;
// User supplies IER masks
const Hwi.MaskingOption_LOWER;
// All current and lower priority
interrupts are disabled. Only a few
targets/devices truly support this
masking option. For those that don't,
this setting is treated the same as
MaskingOption_SELF
C SYNOPSIS
struct Hwi.CCR |
|
NVIC Configuration Control Register (CCR)
XDCscript usage |
meta-domain |
var obj = new Hwi.CCR;
obj.STKALIGN = Bits8 ...
// Auto stack alignment in exception
obj.BFHFNMIGN = Bits8 ...
// All faults ignore BUS Faults
obj.DIV_0_TRP = Bits8 ...
// Trap on divige be zero
obj.UNALIGN_TRP = Bits8 ...
// Trap on all unaligned accesses
obj.USERSETMPEND = Bits8 ...
// Allow user to trigger interrupts
obj.NONEBASETHRDENA = Bits8 ...
// Allow entering thread mode anytime
C SYNOPSIS
struct Hwi.ExcContext |
|
Exception Context - Register contents at the time of an exception
XDCscript usage |
meta-domain |
var obj = new Hwi.ExcContext;
obj.threadHandle = Ptr ...
obj.threadStack = Ptr ...
obj.threadStackSize = SizeT ...
obj.r0 = Ptr ...
obj.r1 = Ptr ...
obj.r2 = Ptr ...
obj.r3 = Ptr ...
obj.r4 = Ptr ...
obj.r5 = Ptr ...
obj.r6 = Ptr ...
obj.r7 = Ptr ...
obj.r8 = Ptr ...
obj.r9 = Ptr ...
obj.r10 = Ptr ...
obj.r11 = Ptr ...
obj.r12 = Ptr ...
obj.sp = Ptr ...
obj.lr = Ptr ...
obj.pc = Ptr ...
obj.psr = Ptr ...
obj.ICSR = Ptr ...
obj.MMFSR = Ptr ...
obj.BFSR = Ptr ...
obj.UFSR = Ptr ...
obj.HFSR = Ptr ...
obj.DFSR = Ptr ...
obj.MMAR = Ptr ...
obj.BFAR = Ptr ...
obj.AFSR = Ptr ...
C SYNOPSIS
struct Hwi.HookSet |
|
Hwi hook set type definition
XDCscript usage |
meta-domain |
var obj = new Hwi.HookSet;
obj.registerFxn = Void(*)(Int) ...
DETAILS
The functions that make up a hookSet have certain restrictions. They
cannot call any Hwi instance functions other than Hwi_getHookContext()
and Hwi_setHookContext(). For all practical purposes, they should treat
the Hwi_Handle passed to these functions as an opaque handle.
C SYNOPSIS
struct Hwi.NVIC |
|
Nested Vectored Interrupt Controller
XDCscript usage |
meta-domain |
var obj = new Hwi.NVIC;
obj.RES_00 = UInt32 ...
// 0xE000E000 reserved
obj.ICTR = UInt32 ...
// 0xE000E004 Interrupt Control Type
obj.RES_08 = UInt32 ...
// 0xE000E008 reserved
obj.RES_0C = UInt32 ...
// 0xE000E00C reserved
obj.STCSR = UInt32 ...
// 0xE000E010 SysTick Control & Status Register
obj.STRVR = UInt32 ...
// 0xE000E014 SysTick Reload Value Register
obj.STCVR = UInt32 ...
// 0xE000E018 SysTick Current Value Register
obj.STCALIB = UInt32 ...
// 0xE000E01C SysTick Calibration Value Register
obj.RES_20 = UInt32[56] ...
// 0xE000E020-0xE000E0FC reserved
obj.ISER = UInt32[8] ...
// 0xE000E100-0xE000E11C Interrupt Set Enable Registers
obj.RES_120 = UInt32[24] ...
// 0xE000E120-0xE000E17C reserved
obj.ICER = UInt32[8] ...
// 0xE000E180-0xE000E19C Interrupt Clear Enable Registers
obj.RES_1A0 = UInt32[24] ...
// 0xE000E1A0-0xE000E1FC reserved
obj.ISPR = UInt32[8] ...
// 0xE000E200-0xE000E21C Interrupt Set Pending Registers
obj.RES_220 = UInt32[24] ...
// 0xE000E220-0xE000E7C reserved
obj.ICPR = UInt32[8] ...
// 0xE000E280-0xE000E29C Interrupt Clear Pending Registers
obj.RES_2A0 = UInt32[24] ...
// 0xE000E2A0-0xE000E2FC reserved
obj.IABR = UInt32[8] ...
// 0xE000E300-0xE000E31C Interrupt Active Bit Registers
obj.RES_320 = UInt32[56] ...
// 0xE000E320-0xE000E3FC reserved
obj.IPR = UInt8[240] ...
// 0xE000E400-0xE000E4EF Interrupt Priority Registers
obj.RES_4F0 = UInt32[516] ...
// 0xE000E4F0-0xE000ECFC reserved
obj.CPUIDBR = UInt32 ...
// 0xE000ED00 CPUID Base Register
obj.ICSR = UInt32 ...
// 0xE000ED04 Interrupt Control State Register
obj.VTOR = UInt32 ...
// 0xE000ED08 Vector Table Offset Register
obj.AIRCR = UInt32 ...
// 0xE000ED0C Application Interrupt/Reset Control Register
obj.SCR = UInt32 ...
// 0xE000ED10 System Control Register
obj.CCR = UInt32 ...
// 0xE000ED14 Configuration Control Register
obj.SHPR = UInt8[12] ...
// 0xE000ED18 System Handlers 4-15 Priority Registers
obj.SHCSR = UInt32 ...
// 0xE000ED24 System Handler Control & State Register
obj.MMFSR = UInt8 ...
// 0xE000ED28 Memory Manage Fault Status Register
obj.BFSR = UInt8 ...
// 0xE000ED29 Bus Fault Status Register
obj.UFSR = UInt16 ...
// 0xE000ED2A Usage Fault Status Register
obj.HFSR = UInt32 ...
// 0xE000ED2C Hard Fault Status Register
obj.DFSR = UInt32 ...
// 0xE000ED30 Debug Fault Status Register
obj.MMAR = UInt32 ...
// 0xE000ED34 Memory Manager Address Register
obj.BFAR = UInt32 ...
// 0xE000ED38 Bus Fault Address Register
obj.AFSR = UInt32 ...
// 0xE000ED3C Auxiliary Fault Status Register
obj.PFR0 = UInt32 ...
// 0xE000ED40 Processor Feature Register
obj.PFR1 = UInt32 ...
// 0xE000ED44 Processor Feature Register
obj.DFR0 = UInt32 ...
// 0xE000ED48 Debug Feature Register
obj.AFR0 = UInt32 ...
// 0xE000ED4C Auxiliary Feature Register
obj.MMFR0 = UInt32 ...
// 0xE000ED50 Memory Model Fault Register0
obj.MMFR1 = UInt32 ...
// 0xE000ED54 Memory Model Fault Register1
obj.MMFR2 = UInt32 ...
// 0xE000ED58 Memory Model Fault Register2
obj.MMFR3 = UInt32 ...
// 0xE000ED5C Memory Model Fault Register3
obj.ISAR0 = UInt32 ...
// 0xE000ED60 ISA Feature Register0
obj.ISAR1 = UInt32 ...
// 0xE000ED64 ISA Feature Register1
obj.ISAR2 = UInt32 ...
// 0xE000ED68 ISA Feature Register2
obj.ISAR3 = UInt32 ...
// 0xE000ED6C ISA Feature Register3
obj.ISAR4 = UInt32 ...
// 0xE000ED70 ISA Feature Register4
obj.RES_D74 = UInt32[99] ...
// 0xE000ED74-0xE000EEFC reserved
obj.STI = UInt32 ...
// 0xE000EF00 Software Trigger Interrupt Register
obj.PID4 = UInt32 ...
// 0xE000EFD0 Peripheral ID Register4
obj.PID5 = UInt32 ...
// 0xE000EFD4 Peripheral ID Register5
obj.PID6 = UInt32 ...
// 0xE000EFD8 Peripheral ID Register6
obj.PID7 = UInt32 ...
// 0xE000EFDC Peripheral ID Register7
obj.PID0 = UInt32 ...
// 0xE000EFE0 Peripheral ID Register0
obj.PID1 = UInt32 ...
// 0xE000EFE4 Peripheral ID Register1
obj.PID2 = UInt32 ...
// 0xE000EFE8 Peripheral ID Register2
obj.PID3 = UInt32 ...
// 0xE000EFEC Peripheral ID Register3
obj.CID0 = UInt32 ...
// 0xE000EFF0 Component ID Register0
obj.CID1 = UInt32 ...
// 0xE000EFF4 Component ID Register1
obj.CID2 = UInt32 ...
// 0xE000EFF8 Component ID Register2
obj.CID3 = UInt32 ...
// 0xE000EFFC Component ID Register3
C SYNOPSIS
metaonly struct Hwi.NonDispatchedInterrupt |
|
non-dispatched interrupt object.
provided so that XGCONF users can easily plug non-dispatched interrupts
XDCscript usage |
meta-domain |
var obj = new Hwi.NonDispatchedInterrupt;
obj.intNum = Int ...
obj.vfxn = Void(*)(Void) ...
obj.priority = UInt ...
obj.enableInt = Bool ...
config Hwi.NUM_INTERRUPTS // module-wide |
|
The Cortex M3 NVIC supports up to 256 interrupts/exceptions
XDCscript usage |
meta-domain |
const Hwi.NUM_INTERRUPTS = Int computed value;
DETAILS
The actual number supported is device specific and provided by
the catalog device specification.
C SYNOPSIS
config Hwi.NUM_PRIORITIES // module-wide |
|
The Cortex M3 NVIC supports up to 256 interrupt priorities
XDCscript usage |
meta-domain |
const Hwi.NUM_PRIORITIES = Int computed value;
DETAILS
The actual number supported is device specific and provided by
the catalog device specification.
C SYNOPSIS
config Hwi.A_unsupportedMaskingOption // module-wide |
|
Assert when bad maskSetting parameter provided
XDCscript usage |
meta-domain |
msg: "A_unsupportedMaskingOption: unsupported maskSetting."
};
C SYNOPSIS
config Hwi.E_NMI // module-wide |
|
Error raised when NMI exception occurs
XDCscript usage |
meta-domain |
C SYNOPSIS
config Hwi.E_alreadyDefined // module-wide |
|
Error raised when Hwi is already defined
XDCscript usage |
meta-domain |
msg: "E_alreadyDefined: Hwi already defined: intr# %d"
};
C SYNOPSIS
config Hwi.E_busFault // module-wide |
|
Error raised when bus fault exception occurs
XDCscript usage |
meta-domain |
C SYNOPSIS
config Hwi.E_debugMon // module-wide |
|
Error raised when debugMon exception occurs
XDCscript usage |
meta-domain |
C SYNOPSIS
config Hwi.E_exception // module-wide |
|
Error raised when an exception occurs
XDCscript usage |
meta-domain |
msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
};
C SYNOPSIS
config Hwi.E_hardFault // module-wide |
|
Error raised when hard fault exception occurs
XDCscript usage |
meta-domain |
msg: "E_hardFault: %s"
};
C SYNOPSIS
config Hwi.E_memFault // module-wide |
|
Error raised when memory fault exception occurs
XDCscript usage |
meta-domain |
C SYNOPSIS
config Hwi.E_noIsr // module-wide |
|
Error raised when an uninitialized interrupt occurs
XDCscript usage |
meta-domain |
msg: "E_noIsr: id = %d, pc = %08x"
};
C SYNOPSIS
config Hwi.E_reserved // module-wide |
|
Error raised when reserved exception occurs
XDCscript usage |
meta-domain |
msg: "E_reserved: %s %d"
};
C SYNOPSIS
config Hwi.E_svCall // module-wide |
|
Error raised when svCall exception occurs
XDCscript usage |
meta-domain |
msg: "E_svCall: svNum = %d"
};
C SYNOPSIS
config Hwi.E_usageFault // module-wide |
|
Error raised when usage fault exception occurs
XDCscript usage |
meta-domain |
msg: "E_usageFault: %s"
};
C SYNOPSIS
config Hwi.LD_end // module-wide |
|
Issued just after return from Hwi function (with interrupts disabled)
XDCscript usage |
meta-domain |
msg: "LD_end: hwi: 0x%x"
};
C SYNOPSIS
config Hwi.LM_begin // module-wide |
|
Issued just prior to Hwi function invocation (with interrupts disabled)
XDCscript usage |
meta-domain |
msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
};
C SYNOPSIS
config Hwi.disablePriority // module-wide |
|
The priority that BASEPRI is set to by Hwi_disable()
XDCscript usage |
meta-domain |
Hwi.disablePriority = UInt undefined;
DETAILS
All interrupts configured with equal or less priority (equal or
higher number) than disablePriority are disabled by Hwi_disable.
Interrupts configured with higher priority (smaller number) than
disablePriority are non-maskable (ie zero-latency).
The default setting is the second highest interrupt priority
defined for the device. This results in priority 0 (and all
other values in the same priority group) being
the non-maskable interrupt priority. All other priorities
are disabled with Hwi_disable().
C SYNOPSIS
config Hwi.dispatcherAutoNestingSupport // module-wide |
|
Include interrupt nesting logic in interrupt dispatcher?
XDCscript usage |
meta-domain |
Hwi.dispatcherAutoNestingSupport = Bool true;
DETAILS
Default is true.
This option provides the user with the ability to optimize
interrupt dispatcher performance when support for interrupt
nesting is not required.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that manipulates interrupt mask
registers and enables and disables interrupts before and
after invoking the user's Hwi function.
Set this parameter to false if you don't need interrupts
enabled during the execution of your Hwi functions.
C SYNOPSIS
config Hwi.dispatcherIrpTrackingSupport // module-wide |
|
Controls whether the
dispatcher retains the interrupted thread's return address
XDCscript usage |
meta-domain |
Hwi.dispatcherIrpTrackingSupport = Bool true;
DETAILS
This option is enabled by default.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that keeps track of the interrupt's
return address and provide a small savings in interrupt latency.
The application can get an interrupt's most recent return
address using the
getIrp API.
C SYNOPSIS
config Hwi.dispatcherSwiSupport // module-wide |
|
Include Swi scheduling logic in interrupt dispatcher?
XDCscript usage |
meta-domain |
Hwi.dispatcherSwiSupport = Bool undefined;
DETAILS
Default is inherited from
BIOS.swiEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that Swis
will not be posted from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Swi scheduler
prior to returning from an interrupt.
C SYNOPSIS
config Hwi.dispatcherTaskSupport // module-wide |
|
Include Task scheduling logic in interrupt dispatcher?
XDCscript usage |
meta-domain |
Hwi.dispatcherTaskSupport = Bool undefined;
DETAILS
Default is inherited from
BIOS.taskEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that no
Task scheduling APIs (ie
Semaphore_post()) will be executed from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Task scheduler
prior to returning from an interrupt.
C SYNOPSIS
config Hwi.excHookFunc // module-wide |
|
User Exception hook function
XDCscript usage |
meta-domain |
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
C SYNOPSIS
config Hwi.priGroup // module-wide |
|
The PRIGROUP setting. Default is 0
XDCscript usage |
meta-domain |
DETAILS
This value will be written to the PRIGROUP field
within the NVIC's Application Interrupt and Reset Control
Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
values are interpreted by the hardware.
Valid settings are 0-7.
The default setting of 0 causes bits 7-1 of an interrupt's
priority value to be used to as a pre-emption priority, and bit 0
is used to determine which of two simultaneous interrupts with
the same pre-emption priority will be serviced first.
C SYNOPSIS
metaonly config Hwi.busFaultFunc // module-wide |
|
Bus Fault Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.busFaultFunc = Void(*)(Void) undefined;
metaonly config Hwi.common$ // module-wide |
|
Common module configuration parameters
XDCscript usage |
meta-domain |
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
metaonly config Hwi.debugMonFunc // module-wide |
|
Debug Mon Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.debugMonFunc = Void(*)(Void) undefined;
metaonly config Hwi.enableException // module-wide |
|
Enable full exception decoding
XDCscript usage |
meta-domain |
Hwi.enableException = Bool false;
DETAILS
When this is enabled, the exception handler will fully
decode an exception and dump the registers to the
system console.
metaonly config Hwi.excContextBuffer // module-wide |
|
User Exception Context Buffer Address
XDCscript usage |
meta-domain |
Hwi.excContextBuffer = Ptr undefined;
DETAILS
By default, when an exception occurs, an
ExcContext
structure is allocated on the ISR stack and filled in within the
exception handler.
If
excContextBuffer is initialized by the user, the
ExcContext structure will be placed at that address instead.
The buffer must be large enough to contain an
ExcContext
structure.
metaonly config Hwi.excStackBuffer // module-wide |
|
User Exception Stack Buffer Address
XDCscript usage |
meta-domain |
Hwi.excStackBuffer = Ptr undefined;
DETAILS
By default, when an exception occurs, a pointer to the base address
of the stack being used by the thread causing the exception is placed
If
excStackBuffer is initialized by the user, the
stack contents of the thread causing the exception will be
copied to that address instead.
The buffer must be large enough to contain the largest task stack
or ISR stack defined in the application.
metaonly config Hwi.hardFaultFunc // module-wide |
|
Hard Fault Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.hardFaultFunc = Void(*)(Void) undefined;
metaonly config Hwi.memFaultFunc // module-wide |
|
Hard Mem Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.memFaultFunc = Void(*)(Void) undefined;
metaonly config Hwi.nmiFunc // module-wide |
|
NMI Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.nmiFunc = Void(*)(Void) undefined;
metaonly config Hwi.nonDispatchedInterrupts // module-wide |
|
non-dispatched interrupt array.
provided so that XGCONF users can easily plug non-dispatched interrupts
XDCscript usage |
meta-domain |
metaonly config Hwi.nullIsrFunc // module-wide |
|
Uninitialized ISR Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.nullIsrFunc = Void(*)(Void) undefined;
metaonly config Hwi.nvicCCR // module-wide |
|
NVIC CCR register settings
XDCscript usage |
meta-domain |
STKALIGN: 1,
BFHFNMIGN: 0,
DIV_0_TRP: 0,
UNALIGN_TRP: 0,
USERSETMPEND: 0,
NONEBASETHRDENA: 0
};
DETAILS
These setting are written to Hwi_nvic.CCR at startup time.
See the Cortex M3 architecture reference manual for details
on the meanings of these parameters.
metaonly config Hwi.reservedFunc // module-wide |
|
Reserved Exception Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.reservedFunc = Void(*)(Void) undefined;
metaonly config Hwi.resetFunc // module-wide |
|
Reset Handler. Default is c_int00
XDCscript usage |
meta-domain |
Hwi.resetFunc = Void(*)(Void) undefined;
metaonly config Hwi.resetVectorAddress // module-wide |
|
Alternate reset vector address. Default is 0x00000000
XDCscript usage |
meta-domain |
Hwi.resetVectorAddress = Ptr 0x00000000;
DETAILS
if initialized by the user then an additional reset vector
is created and placed in the ".resetVecs" section.
To place the .resetVecs section into a specific memory section,
add the following command to your config script:
Program.sectMap[".resetVecs"] = YourMemorySection;
metaonly config Hwi.rovViewInfo // module-wide |
|
XDCscript usage |
meta-domain |
metaonly config Hwi.svCallFunc // module-wide |
|
SVCall Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.svCallFunc = Void(*)(Void) undefined;
metaonly config Hwi.usageFaultFunc // module-wide |
|
Usage Fault Handler. Default is set to an internal exception handler
XDCscript usage |
meta-domain |
Hwi.usageFaultFunc = Void(*)(Void) undefined;
metaonly config Hwi.vectorTableAddress // module-wide |
|
Location of the Interrupt Vector Table
XDCscript usage |
meta-domain |
Hwi.vectorTableAddress = Ptr 0x00000000;
DETAILS
This parameter allows the user to override the default placement
of the interrupt vector table. The NVIC's Vector Table Offset
Register (VTOR) is also programmed to this value.
By default, the interrupt vector table will be placed at
address 0x00000000.
Some systems require the vector table to be placed at an address
other than 0 but still need a copy of the two M3 boot vectors
(SP and reset PC), located there. To achieve this, a separate
parameter
resetVectorAdress is provided. If the
resetVectorAddress has a different value then the vectorTableAddress
then a separate 2 vector table is generated and placed at that
address.
The vector table must be placed at an address at or lower than
0x3FFFFC00 and must be aligned on an even 64 word boundary.
metaonly Hwi.addHookSet() // module-wide |
|
addHookSet is used in a config file to add a hook set (defined
by struct HookSet)
XDCscript usage |
meta-domain |
ARGUMENTS
hook
structure of type HookSet
DETAILS
HookSet structure elements may be omitted, in which case those
elements will not exist.
Instance Config Parameters |
|
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
// Instance config-params object
params.arg = UArg 0;
// ISR function argument. Default is 0
params.enableInt = Bool true;
// Enable this interrupt now? Default is true
params.eventId = Int -1;
// Interrupt event ID (Interrupt Selection Number)
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored
// The interrupt controller is designed for priority based interrupts
params.priority = Int 255;
// Interrupt priority.
Valid priorities are 0 - 255. 0 is the highest priority.
The default is 255 which is the lowest priority interrupt
config Hwi.arg // instance |
|
ISR function argument. Default is 0
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
...
params.arg = UArg 0;
C SYNOPSIS
config Hwi.enableInt // instance |
|
Enable this interrupt now? Default is true
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
...
params.enableInt = Bool true;
C SYNOPSIS
config Hwi.eventId // instance |
|
Interrupt event ID (Interrupt Selection Number)
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
...
params.eventId = Int -1;
C SYNOPSIS
config Hwi.maskSetting // instance |
|
The interrupt controller is designed for priority based interrupts
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
...
C SYNOPSIS
config Hwi.priority // instance |
|
Interrupt priority.
Valid priorities are 0 - 255. 0 is the highest priority.
The default is 255 which is the lowest priority interrupt
XDCscript usage |
meta-domain |
var params = new Hwi.Params;
...
params.priority = Int 255;
C SYNOPSIS
Instance Creation |
|
XDCscript usage |
meta-domain |
// Allocate instance config-params
params.config = ...
// Assign individual configs
var inst = Hwi.create(Int intNum, Void(*)(UArg) hwiFxn, params);
// Create an instance-object
ARGUMENTS
intNum
interrupt number
hwiFxn
pointer to ISR function
params
per-instance config params, or NULL to select default values (target-domain only)
eb
active error-handling block, or NULL to select default policy (target-domain only)
DETAILS
A Hwi dispatcher table entry is created and filled with the
function specified by the fxn parameter and the attributes
specified by the params parameter.
If params is NULL, the Hwi's dispatcher properties are assigned a
default set of values. Otherwise, the following properties
are specified by a structure of type Hwi_Params.
- The arg element is a generic argument that is passed to the plugged
function as its only parameter. The default value is 0.
- The enableInt element determines whether the interrupt should be
enabled in the IER by create.
- The maskSetting element defines the dispatcherAutoNestingSupport
behavior of the interrupt.
Hwi_create returns a pointer to the created Hwi object.