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33 34 35 36
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44
45 import ti.sysbios.BIOS;
46 import ti.sysbios.interfaces.IHwi;
47
48 /*!
49 * ======== Hwi ========
50 * Cortex M3 Hardware Interrupt Manager.
51 *
52 * The Cortex M3's Nested Vectored Interrupt Controller (NVIC)
53 * supports 256 interrupts/exceptions.
54 *
55 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
56 * to an interrupt's position in the interrupt vector table.
57 *
58 * ID 0 corresponds to vector 0 which is used by the NVIC
59 * to hold the initial (reset) stack pointer value.
60 *
61 * IDs 1-14 are hardwired to exceptions.
62 *
63 * ID 15 is the SysTick timer interrupt.
64 *
65 * ID's 16-255 are mapped to the NVIC's user interrupts 0-239
66 * which are tied to platform specific interrupt sources.
67 *
68 * The M3 Hwi module supports "zero latency" interrupts.
69 * Interrupts configured with priority greater (in priority,
70 * lower in number) than {@link #disablePriority}
71 * are NOT disabled by {@link #disable}.
72 *
73 * Zero latency interrupts are not handled by SYS/BIOS's interrupt
74 * dispatcher. Instead, they are vectored to directly.
75 * As such, and because they are not masked by {@link #disable},
76 * these interrupt handlers are severely restricted in terms of the
77 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY CONSIDERED!
78 *
79 * Due to the M3's native automatic stacking of saved-by-caller C
80 * context on the way to an ISR, zero latency interrupt handlers
81 * are implemented using regular C functions (ie no 'interrupt'
82 * keyword is required).
83 *
84 * Zero latency interrupts are distinguished from regular dispatched
85 * interrupts at create time by their priority being greater than
86 * {@link #disablePriority}.
87 *
88 * Note that since zero latency interrupts don't use the dispatcher,
89 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
90 * functional.
91 *
92 * @a(Restrictions)
93 * When used within a dual M3 core (Ducati) arrangement, care must be
94 * taken when initializing this shared resource.
95 * The "Shared Resources" note provided
96 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
97 * the management of the various hardware and software resources
98 * shared by the two M3 cores.
99 *
100 * By default, core 0 places its runtime vector table at 0x400 and
101 * core 1 places its runtime vector table at 0x800.
102 * This placement is made automatically when the
103 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
104 * This default behavior can be overridden by explicitly setting the
105 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
106 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
107 * @a
108 *
109 * @p(html)
110 * <h3> Calling Context </h3>
111 * <table border="1" cellpadding="3">
112 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
113 *
114 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
115 * <!-- -->
116 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
117 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
118 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
119 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
120 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
121 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
122 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
123 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
124 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
125 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
126 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
127 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
128 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
129 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
130 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
131 * <tr><td colspan="6"> Definitions: <br />
132 * <ul>
133 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
134 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
135 * <li> <b>Task</b>: API is callable from a Task thread. </li>
136 * <li> <b>Main</b>: API is callable during any of these phases: </li>
137 * <ul>
138 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
139 * <li> During xdc.runtime.Startup.lastFxns. </li>
140 * <li> During main().</li>
141 * <li> During BIOS.startupFxns.</li>
142 * </ul>
143 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
144 * <ul>
145 * <li> During xdc.runtime.Startup.firstFxns.</li>
146 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
147 * </ul>
148 * </ul>
149 * </td></tr>
150 *
151 * </table>
152 * @p
153 */
154
155
156 @Template("./Hwi.xdt")
157 @ModuleStartup
158
159 module Hwi inherits ti.sysbios.interfaces.IHwi
160 {
161
162
163 /*!
164 * The Cortex M3 NVIC supports up to 256 interrupts/exceptions.
165 *
166 * The actual number supported is device specific and provided by
167 * the catalog device specification.
168 */
169 readonly config Int NUM_INTERRUPTS;
170
171 /*!
172 * The Cortex M3 NVIC supports up to 256 interrupt priorities.
173 *
174 * The actual number supported is device specific and provided by
175 * the catalog device specification.
176 */
177 readonly config Int NUM_PRIORITIES;
178
179
180
181 /*! Hwi vector function type definition. */
182 typedef Void (*VectorFuncPtr)(void);
183
184 /*! Exception hook function type definition. */
185 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
186
187 /*! NVIC Configuration Control Register (CCR). */
188 struct CCR {
189 Bits8 STKALIGN; /*! Auto stack alignment in exception */
190 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
191 Bits8 DIV_0_TRP; /*! Trap on divige be zero */
192 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
193 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
194 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
195 };
196
197 /*!
198 * Nested Vectored Interrupt Controller.
199 */
200 struct NVIC {
201 UInt32 RES_00; /*! 0xE000E000 reserved */
202 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
203 UInt32 RES_08; /*! 0xE000E008 reserved */
204 UInt32 RES_0C; /*! 0xE000E00C reserved */
205 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
206 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
207 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
208 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
209 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
210 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
211 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
212 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
213 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
214 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
215 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
216 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
217 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
218 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
219 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
220 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
221 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
222 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
223 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
224 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
225 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
226 UInt32 SCR; /*! 0xE000ED10 System Control Register */
227 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
228 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
229 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
230 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
231 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
232 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
233 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
234 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
235 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
236 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
237 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
238 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
239 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
240 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
241 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
242 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
243 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
244 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
245 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
246 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
247 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
248 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
249 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
250 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
251 UInt32 RES_D74[99]; /*! 0xE000ED74-0xE000EEFC reserved */
252 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
253 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
254 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
255 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
256 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
257 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
258 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
259 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
260 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
261 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
262 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
263 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
264 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
265 }
266
267 /*!
268 * Physical Nested Vectored Interrupt Controller Device.
269 * Short name is "Hwi_nvic"
270 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
271 */
272 extern volatile NVIC nvic;
273
274 /*!
275 * Exception Context - Register contents at the time of an exception.
276 */
277 struct ExcContext {
278
279 BIOS.ThreadType threadType;
280
281 Ptr threadHandle;
282
283 Ptr threadStack;
284
285
286 SizeT threadStackSize;
287
288
289 Ptr r0;
290 Ptr r1;
291 Ptr r2;
292 Ptr r3;
293 Ptr r4;
294 Ptr r5;
295 Ptr r6;
296 Ptr r7;
297 Ptr r8;
298 Ptr r9;
299 Ptr r10;
300 Ptr r11;
301 Ptr r12;
302 Ptr sp;
303 Ptr lr;
304 Ptr pc;
305 Ptr psr;
306
307
308 Ptr ICSR;
309 Ptr MMFSR;
310 Ptr BFSR;
311 Ptr UFSR;
312 Ptr HFSR;
313 Ptr DFSR;
314 Ptr MMAR;
315 Ptr BFAR;
316 Ptr AFSR;
317 }
318
319 /*! @_nodoc */
320 metaonly struct BasicView {
321 Ptr halHwiHandle;
322 String label;
323 Int intNum;
324 Int priority;
325 Int group;
326 Int subPriority;
327 String fxn;
328 UArg arg;
329 };
330
331 /*! @_nodoc */
332 metaonly struct DetailedView {
333 Ptr halHwiHandle;
334 String label;
335 Int intNum;
336 Int priority;
337 Int group;
338 Int subPriority;
339 String fxn;
340 UArg arg;
341 Ptr irp;
342 String status;
343 };
344
345 /*! @_nodoc */
346 metaonly struct ModuleView {
347 String options[4];
348 String activeInterrupt;
349 String pendingInterrupt;
350 String exception;
351 SizeT hwiStackPeak;
352 SizeT hwiStackSize;
353 Ptr hwiStackBase;
354 };
355
356 @Facet
357 metaonly config ViewInfo.Instance rovViewInfo =
358 ViewInfo.create({
359 viewMap: [
360 ['Basic',
361 {
362 type: ViewInfo.INSTANCE,
363 viewInitFxn: 'viewInitBasic',
364 structName: 'BasicView'
365 }
366 ],
367 ['Detailed',
368 {
369 type: ViewInfo.INSTANCE,
370 viewInitFxn: 'viewInitDetailed',
371 structName: 'DetailedView'
372 }
373 ],
374 ['Module',
375 {
376 type: ViewInfo.MODULE,
377 viewInitFxn: 'viewInitModule',
378 structName: 'ModuleView'
379 }
380 ],
381 ['Exception',
382 {
383 type: ViewInfo.TREE,
384 viewInitFxn: 'viewInitException',
385 structName: 'ExcContext'
386 }
387 ]
388 ]
389 });
390
391
392
393
394
395 /*!
396 * Issued just prior to Hwi function invocation (with interrupts disabled)
397 */
398 config Log.Event LM_begin = {
399 mask: Diags.USER1 | Diags.USER2,
400 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
401 };
402
403 /*!
404 * Issued just after return from Hwi function (with interrupts disabled)
405 */
406 config Log.Event LD_end = {
407 mask: Diags.USER2,
408 msg: "LD_end: hwi: 0x%x"
409 };
410
411
412
413 /*! Assert when bad maskSetting parameter provided */
414 config Assert.Id A_unsupportedMaskingOption = {
415 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
416 };
417
418
419
420 /*!
421 * Error raised when Hwi is already defined
422 */
423 config Error.Id E_alreadyDefined = {
424 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
425 };
426
427 /*!
428 * Error raised when an exception occurs
429 */
430 config Error.Id E_exception = {
431 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
432 };
433
434 /*!
435 * Error raised when an uninitialized interrupt occurs
436 */
437 config Error.Id E_noIsr = {
438 msg: "E_noIsr: id = %d, pc = %08x"
439 };
440
441 /*!
442 * Error raised when NMI exception occurs
443 */
444 config Error.Id E_NMI = {
445 msg: "E_NMI: %s"
446 };
447
448 /*!
449 * Error raised when hard fault exception occurs
450 */
451 config Error.Id E_hardFault = {
452 msg: "E_hardFault: %s"
453 };
454
455 /*!
456 * Error raised when memory fault exception occurs
457 */
458 config Error.Id E_memFault = {
459 msg: "E_memFault: %s"
460 };
461
462 /*!
463 * Error raised when bus fault exception occurs
464 */
465 config Error.Id E_busFault = {
466 msg: "E_busFault: %s"
467 };
468
469 /*!
470 * Error raised when usage fault exception occurs
471 */
472 config Error.Id E_usageFault = {
473 msg: "E_usageFault: %s"
474 };
475
476 /*!
477 * Error raised when svCall exception occurs
478 */
479 config Error.Id E_svCall = {
480 msg: "E_svCall: svNum = %d"
481 };
482
483 /*!
484 * Error raised when debugMon exception occurs
485 */
486 config Error.Id E_debugMon = {
487 msg: "E_debugMon: %s"
488 };
489
490 /*!
491 * Error raised when reserved exception occurs
492 */
493 config Error.Id E_reserved = {
494 msg: "E_reserved: %s %d"
495 };
496
497
498
499 /*!
500 * Location of the Interrupt Vector Table
501 *
502 * This parameter allows the user to override the default placement
503 * of the interrupt vector table. The NVIC's Vector Table Offset
504 * Register (VTOR) is also programmed to this value.
505 *
506 * By default, the interrupt vector table will be placed at
507 * address 0x00000000.
508 *
509 * Some systems require the vector table to be placed at an address
510 * other than 0 but still need a copy of the two M3 boot vectors
511 * (SP and reset PC), located there. To achieve this, a separate
512 * parameter {@link #resetVectorAdress} is provided. If the
513 * resetVectorAddress has a different value then the vectorTableAddress
514 * then a separate 2 vector table is generated and placed at that
515 * address.
516 *
517 * The vector table must be placed at an address at or lower than
518 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
519 */
520 metaonly config Ptr vectorTableAddress = 0x00000000;
521
522 /*!
523 * Alternate reset vector address. Default is 0x00000000
524 *
525 * if initialized by the user then an additional reset vector
526 * is created and placed in the ".resetVecs" section.
527 * To place the .resetVecs section into a specific memory section,
528 * add the following command to your config script:
529 * @p(code)
530 * Program.sectMap[".resetVecs"] = YourMemorySection;
531 * @p
532 */
533 metaonly config Ptr resetVectorAddress = 0x00000000;
534
535 /*! Reset Handler. Default is c_int00 */
536 metaonly config VectorFuncPtr resetFunc;
537
538 /*! NMI Handler. Default is set to an internal exception handler */
539 metaonly config VectorFuncPtr nmiFunc;
540
541 /*! Hard Fault Handler. Default is set to an internal exception handler */
542 metaonly config VectorFuncPtr hardFaultFunc;
543
544 /*! Hard Mem Handler. Default is set to an internal exception handler */
545 metaonly config VectorFuncPtr memFaultFunc;
546
547 /*! Bus Fault Handler. Default is set to an internal exception handler */
548 metaonly config VectorFuncPtr busFaultFunc;
549
550 /*! Usage Fault Handler. Default is set to an internal exception handler */
551 metaonly config VectorFuncPtr usageFaultFunc;
552
553 /*! SVCall Handler. Default is set to an internal exception handler */
554 metaonly config VectorFuncPtr svCallFunc;
555
556 /*! Debug Mon Handler. Default is set to an internal exception handler */
557 metaonly config VectorFuncPtr debugMonFunc;
558
559 /*! Reserved Exception Handler. Default is set to an internal exception handler */
560 metaonly config VectorFuncPtr reservedFunc;
561
562 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
563 metaonly config VectorFuncPtr nullIsrFunc;
564
565 /*!
566 * Enable full exception decoding
567 *
568 * When this is enabled, the exception handler will fully
569 * decode an exception and dump the registers to the
570 * system console.
571 */
572 metaonly config Bool enableException = false;
573
574 /*!
575 * User Exception Context Buffer Address
576 *
577 * By default, when an exception occurs, an {@link #ExcContext}
578 * structure is allocated on the ISR stack and filled in within the
579 * exception handler.
580 *
581 * If {@link #excContextBuffer} is initialized by the user, the
582 * {@link #ExcContext} structure will be placed at that address instead.
583 *
584 * The buffer must be large enough to contain an {@link #ExcContext}
585 * structure.
586 */
587 metaonly config Ptr excContextBuffer;
588
589 /*!
590 * User Exception Stack Buffer Address
591 *
592 * By default, when an exception occurs, a pointer to the base address
593 * of the stack being used by the thread causing the exception is placed
594 *
595 * If {@link #excStackBuffer} is initialized by the user, the
596 * stack contents of the thread causing the exception will be
597 * copied to that address instead.
598 *
599 * The buffer must be large enough to contain the largest task stack
600 * or ISR stack defined in the application.
601 */
602 metaonly config Ptr excStackBuffer;
603
604
605 /*!
606 * User Exception hook function.
607 *
608 * Called just after the exception context has been initialized.
609 *
610 * This function will be run on the ISR stack.
611 *
612 * This function must run to completion.
613 *
614 * It is called without any Task or Swi scheduling protection
615 * and therefore can not call any functions that may cause a Swi or Task
616 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
617 */
618 config ExceptionHookFuncPtr excHookFunc = null;
619
620 /*!
621 * NVIC CCR register settings
622 *
623 * These setting are written to Hwi_nvic.CCR at startup time.
624 *
625 * See the Cortex M3 architecture reference manual for details
626 * on the meanings of these parameters.
627 */
628 metaonly config CCR nvicCCR = {
629 STKALIGN: 1,
630 BFHFNMIGN: 0,
631 DIV_0_TRP: 0,
632 UNALIGN_TRP: 0,
633 USERSETMPEND: 0,
634 NONEBASETHRDENA: 0
635 };
636
637 /*!
638 * The priority that BASEPRI is set to by Hwi_disable().
639 *
640 * All interrupts configured with equal or less priority (equal or
641 * higher number) than disablePriority are disabled by Hwi_disable.
642 * Interrupts configured with higher priority (smaller number) than
643 * disablePriority are non-maskable (ie zero-latency).
644 *
645 * The default setting is the second highest interrupt priority
646 * defined for the device. This results in priority 0 (and all
647 * other values in the same priority group) being
648 * the non-maskable interrupt priority. All other priorities
649 * are disabled with Hwi_disable().
650 */
651 config UInt disablePriority;
652
653 /*!
654 * The PRIGROUP setting. Default is 0.
655 *
656 * This value will be written to the PRIGROUP field
657 * within the NVIC's Application Interrupt and Reset Control
658 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
659 * values are interpreted by the hardware.
660 *
661 * Valid settings are 0-7.
662 *
663 * The default setting of 0 causes bits 7-1 of an interrupt's
664 * priority value to be used to as a pre-emption priority, and bit 0
665 * is used to determine which of two simultaneous interrupts with
666 * the same pre-emption priority will be serviced first.
667 */
668 config UInt priGroup = 0;
669
670 /*!
671 * non-dispatched interrupt object.
672 * provided so that XGCONF users can easily plug non-dispatched interrupts
673 */
674 metaonly struct NonDispatchedInterrupt {
675 Int intNum;
676 VectorFuncPtr vfxn;
677 UInt priority;
678 Bool enableInt;
679 };
680
681 /*!
682 * non-dispatched interrupt array.
683 * provided so that XGCONF users can easily plug non-dispatched interrupts
684 */
685 metaonly config NonDispatchedInterrupt nonDispatchedInterrupts[string];
686
687
688
689 /*!
690 * ======== disable ========
691 */
692 @DirectCall
693 override UInt disable();
694
695 /*!
696 * ======== enable ========
697 */
698 @DirectCall
699 override UInt enable();
700
701 /*!
702 * ======== restore ========
703 */
704 @DirectCall
705 override Void restore(UInt key);
706
707 /*!
708 * ======== disableInterrupt ========
709 */
710 @DirectCall
711 override UInt disableInterrupt(UInt intNum);
712
713 /*!
714 * ======== enableInterrupt ========
715 */
716 @DirectCall
717 override UInt enableInterrupt(UInt intNum);
718
719 /*!
720 * ======== restore ========
721 */
722 @DirectCall
723 override Void restoreInterrupt(UInt intNum, UInt key);
724
725 /*!
726 * ======== inUseMeta ========
727 * @_nodoc
728 * Check for Hwi already in use.
729 * For internal SYS/BIOS use only.
730 * Should be called prior to any internal Hwi.create().
731 *
732 * @param(intNum) interrupt number
733 */
734 metaonly Bool inUseMeta(UInt intNum);
735
736 /*!
737 * @_nodoc
738 * ======== plug ========
739 * Plug a non dispatched interrupt vector with an ISR address.
740 *
741 * @param(intNum) interrupt number
742 * @param(fxn) pointer to ISR function
743 */
744 @DirectCall
745 Void plug(UInt intNum, VectorFuncPtr fxn);
746
747 /*!
748 * ======== getHandle ========
749 * Returns Hwi_handle associated with intNum
750 *
751 * @param(intNum) interrupt number
752 */
753 @DirectCall
754 Handle getHandle(UInt intNum);
755
756 /*!
757 * ======== setPriority ========
758 * Set an interrupt's relative priority.
759 *
760 * Valid priorities are 0 - 255. 0 is highest priority.
761 *
762 * @param(intNum) ID of interrupt
763 * @param(priority) priority
764 */
765 @DirectCall
766 Void setPriority(UInt intNum, UInt priority);
767
768 /*!
769 * ======== excSetBuffers ========
770 * Set the exception context and stack buffer pointers
771 *
772 * @param(excContextBuffer) Address to place ExcContext
773 * @param(excStackBuffer) Address to place ExcStack
774 */
775 @DirectCall
776 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
777
778 /*! @_nodoc
779 * ======== allowInterrupts ========
780 * WA 1.1 function to briefly enable interrupts
781 */
782 @DirectCall
783 Void allowInterrupts_wa1_1();
784
785 instance:
786
787 /*!
788 * Interrupt priority.
789 * Valid priorities are 0 - 255. 0 is the highest priority.
790 * The default is 255 which is the lowest priority interrupt.
791 */
792 override config Int priority = 255;
793
794 /*! The interrupt controller is designed for priority based interrupts */
795 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
796
797 /*!
798 * ======== reconfig ========
799 * Reconfigure a dispatched interrupt.
800 */
801 @DirectCall
802 Void reconfig(FuncPtr fxn, const Params *params);
803
804 internal:
805
806 807 808 809 810 811 812 813 814
815 metaonly config Bool enableWA1_1 = false;
816
817 818 819 820 821 822
823 config UInt (*swiDisable)();
824 config Void (*swiRestoreHwi)(UInt);
825 config UInt (*taskDisable)();
826 config Void (*taskRestoreHwi)(UInt);
827
828
829 config UInt32 ccr;
830
831 /*!
832 * const array to hold all HookSet objects.
833 */
834 config HookSet hooks[length] = [];
835
836
837
838 Void beginHook_wa1_1(IHwi.Handle hwi);
839
840 /*!
841 * ======== initVTOR ========
842 * Initialize the Vector Table Offset Register
843 * This function is plugged as a Startup.firstFxn
844 * to set up vector table as early as possible
845 */
846 Void initVTOR();
847
848 /*!
849 * ======== excHandlerAsm ========
850 * asm code exception handler
851 */
852 Void excHandlerAsm();
853
854 /*!
855 * ======== excHandler ========
856 * exception Handler routes to
857 * either min or max exception handler
858 */
859 Void excHandler(UInt *excStack, UInt lr);
860
861 /*!
862 * ======== excHandlerMin ========
863 * Minimal Exception Handler
864 */
865 Void excHandlerMin(UInt *excStack, UInt lr);
866
867 /*!
868 * ======== excHandlerMax ========
869 * Full Featured Exception Handler
870 */
871 Void excHandlerMax(UInt *excStack, UInt lr);
872
873 /*! Hwi exception handler function type definition. */
874 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
875
876 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMin;
877
878 /*!
879 * ======== excFillContext ========
880 */
881 Void excFillContext();
882
883 /*!
884 * ======== excNmi ========
885 */
886 Void excNmi(UInt *excStack);
887
888 /*!
889 * ======== excHardFault ========
890 */
891 Void excHardFault(UInt *excStack);
892
893 /*!
894 * ======== excMemFault ========
895 */
896 Void excMemFault(UInt *excStack);
897
898 /*!
899 * ======== excBusFault ========
900 */
901 Void excBusFault(UInt *excStack);
902
903 /*!
904 * ======== excUsageFault ========
905 */
906 Void excUsageFault(UInt *excStack);
907
908 /*!
909 * ======== excSvCall ========
910 */
911 Void excSvCall(UInt *excStack);
912
913 /*!
914 * ======== excDebugMon ========
915 */
916 Void excDebugMon(UInt *excStack);
917
918 /*!
919 * ======== excReserved ========
920 */
921 Void excReserved(UInt *excStack, UInt excNum);
922
923 /*!
924 * ======== excNoIsr ========
925 */
926 Void excNoIsr(UInt *excStack, UInt excNum);
927
928 /*!
929 * ======== excDumpRegs ========
930 */
931 Void excDumpRegs(UInt lr);
932
933 /*!
934 * ======== pendSV ========
935 * Used by dispatcher
936 */
937 Void pendSV();
938
939 /*!
940 * ======== init ========
941 * set up Hwi stack
942 */
943 Void init();
944
945 /*! Hwi vector function type definition. */
946 typedef Void (*HandlerFuncPtr)(Handle, UInt);
947
948
949 Void dispatch();
950
951
952 UInt dispatchC(Irp irp);
953
954
955 Void doSwiTaskRestore(UInt tskKey);
956
957 /*! Meta World Only Hwi Configuration Object. */
958 metaonly struct InterruptObj {
959 String name;
960 Bool used;
961 Bool useDispatcher;
962 UInt priority;
963 FuncPtr fxn;
964 VectorFuncPtr vfxn;
965 };
966
967 /*!
968 * Meta-only array of interrupt objects.
969 * This meta-only array of Hwi config objects is initialized
970 * in Hwi.xs:module$meta$init().
971 */
972 metaonly config InterruptObj interrupt[];
973
974 struct Instance_State {
975 UArg arg;
976 FuncPtr fxn;
977 Int intNum;
978 Irp irp;
979 Ptr hookEnv[];
980 };
981
982 struct Module_State {
983 Bits16 enables;
984
985 Bits32 iser[8];
986 UInt8 priorities[];
987 Char *taskSP;
988
989 Bool excActive;
990 ExcContext *excContext;
991 Ptr excStack;
992
993
994 Ptr isrStack;
995 Ptr isrStackBase;
996 SizeT isrStackSize;
997 Ptr vectorTableBase;
998 Handle dispatchTable[];
999 };
1000 }
1001 1002 1003 1004
1005