ARM C/C++ Code Generation Tools v18.1.8.LTS Release Notes

Table of Contents

1 Support Information

1.1 List of Resolved and Known Defects

Resolved defects

ID Summary
CODEGEN-7227 Compiler incorrectly optimizes unsigned loop counter which wraps around
CODEGEN-7146 Compiler loses conversion to size_t in length argument to memcpy
CODEGEN-7011 Compiler intermittently fails with INTERNAL ERROR: opt2000 experienced a segmentation fault
CODEGEN-6914 Enum type with no enumerators fails to emit DW_AT_byte_size, crashes CCS
CODEGEN-6909 Compiler mistakenly reorders and combines conditional definitions of volatile objects
CODEGEN-6866 Compiler computes wrong offset for structure member, causing CCS to display it incorrectly
CODEGEN-6783 Ensure C std headers do not issue MISRA warnings
CODEGEN-6757 Use of C++ lambda causes Dwarf debug information to be incorrect, and prevents debugging the code
CODEGEN-6710 MOVT/MOVW without # on constant causes assembler crash INTERNAL ERROR!: failed to locate symbol for relocation entry at offset
CODEGEN-6690 Stack usage incorrect on many hand-coded assembly library functions

Open defects

ID Summary
CODEGEN-6509 Compiler error: no instance of function template matches the argument list
CODEGEN-6070 Erroneous “redeclared with incompatible type” involving two tagless structs with same form
CODEGEN-5179 When a symbol is remapped, DW_TAG_TI_branch/DW_AT_name is not updated
CODEGEN-5078 Simple syntax error causes assembler to fail with INTERNAL ERROR
CODEGEN-4985 Typo on ULP Advisor message
CODEGEN-4943 MISRA 12.2 is incorrectly issued when one variable is used multiple times as an array index in the same expression
CODEGEN-4934 Incorrect issue MISRA diagnostic 10.5: If the bitwise operators ~ and << are applied
CODEGEN-4789 Compiler incorrectly issues MISRA diagnostic 12.7 Bitwise operators shall not be applied to operands whose underlying type is signed
CODEGEN-4712 No MISRA 10.1 and 10.6 diagnostics issued on initializations
CODEGEN-4346 MISRA 19.4 error fails to identify itself as MISRA diagnostic when problem is on the command line
CODEGEN-4304 C++ feature causes runtime failure on unaligned access on ARM9
CODEGEN-4298 Internal error when passing a temporary array of objects
CODEGEN-4297 Cannot take the address of std::ctype<char>::table_size
CODEGEN-4296 Undefined symbol isblank with -g or -ooff
CODEGEN-4290 wstring runtime failure - likely bug in swprintf
CODEGEN-4281 Unexpected type returned by bitset [] operator
CODEGEN-4276 std::multimap::clear is not noexcept
CODEGEN-4275 std::num_get does not parse floating-point strings correctly
CODEGEN-4259 noexcept(typeid(d)) runtime fail on polymorphic class type
CODEGEN-4258 deeply nested lambda functions hang the codegen
CODEGEN-4250 regex_constants::ECMAScript not expected to be 0
CODEGEN-4248 armcl allows non-default arguments to be specified after default arguments
CODEGEN-4247 Internal error when assigning default arguments to a parameter pack
CODEGEN-4246 armcl allows illegal attribute in friend declarations
CODEGEN-4245 Multiple non-variables may be declared using auto or decltype(auto)
CODEGEN-4244 armcl errors on legal constexpr constructor call
CODEGEN-4234 No error generated for lambda-expression in default argument cannot capture any entity.
CODEGEN-4228 armcl fails to flag an inconsistent use of alignas between a declaration and definition of an object
CODEGEN-4203 Parser errors on empty enum declaration
CODEGEN-4158 TI compiler does not emit clang error: constexpr function never produces a constant expression
CODEGEN-4157 error with using constexpr for return from end() with empty std::initializer_list
CODEGEN-4132 cannot find matching “==” operator definition
CODEGEN-4124 Failure to defer access control checks
CODEGEN-4122 decltype cannot be used as a destructor name
CODEGEN-4119 user-supplied allocator function is not called
CODEGEN-4105 cannot find definition of “>=” operator
CODEGEN-4099 Composing operations for valarray may fail to compile
CODEGEN-4091 Incomplete class type when using various members of <iterator>
CODEGEN-4090 Unimplemented core issue 475: std::uncaught_exception is not true when constructing the thrown object
CODEGEN-4084 assembler errors with bogus .iendfunc asm directive when using –c_src_interlist
CODEGEN-4076 Exception propagating out of noexcept function does not call std::terminate
CODEGEN-4072 Unimplemented core issue 1769: Catching a thrown derived class by reference to base clas
CODEGEN-4071 <regex> never throws error_ctype
CODEGEN-4069 std::linear_congruential_engine doesn't support 8-bit results
CODEGEN-4058 std::function<T>::target_type() should return typeid(void) if target is empty
CODEGEN-4050 shared_ptr::get_deleter() should return the original deleter class without copying
CODEGEN-4044 libcxx istreambuf_iterator points to end of string instead of character past match
CODEGEN-4035 Compiler allows constant subtraction between pointers to different objects
CODEGEN-4032 wofstream << operator unexpected termination
CODEGEN-4026 Non-standard partial ordering of variadic template partial specialization
CODEGEN-4015 Access of const static member through pointer is not a constant expression.
CODEGEN-4002 Undefined behavior on lambda capturing constexpr by reference
CODEGEN-4001 Unimplemented core issue 588: Unqualified name lookup examines dependent base class
CODEGEN-4000 Core 1601: Overload resolution for enum with fixed type
CODEGEN-3999 Unimplemented core issue 1374: Conversion sequence ranks qualification before reference binding
CODEGEN-3998 Unimplemented core issue 1951: cv-qualified void and scalar types are not literal types
CODEGEN-3993 Constant initialiation may take place before dynamic initialization
CODEGEN-3991 We do not issue diagnostics if an allocation function throws a non bad_alloc exception
CODEGEN-3966 slice_array assignment failures
CODEGEN-3965 Invalid conversion on static_cast from T1 to rvalue reference of T2
CODEGEN-3964 Unimplemented core issue 1467: Overloads and initializations with single-element initializer_list
CODEGEN-3963 Unimplemented core issue 591: Name lookup in dependent base class that is also the current instantiation
CODEGEN-3962 Core Issue 1804 unimplemented: friend declaration does not apply to class template specializations
CODEGEN-3961 Pack expansion in template parameter list fails
CODEGEN-3959 std::reference_wrapper doesn't define argument_type for classes containing a typedef member named argument_type
CODEGEN-3954 Problem with std::swap and <tuple>
CODEGEN-3953 scoped_allocator_adaptor can't be explicitly instantiated with two arguments
CODEGEN-3951 Spurious error on bypassing initialization of trivially constructible objects
CODEGEN-3948 Spurious syntax error on alignas in alias declaration
CODEGEN-3947 Spurious error on unevaluated use of undefined constexpr function
CODEGEN-3946 Spurious error on global qualifier of struct template
CODEGEN-3944 Raw string d-char-sequence isn't supported
CODEGEN-3941 operator<<(std::basic_ostream<K,T>&, const std::error_code&) is not defined in system_error
CODEGEN-3938 std::rethrow_if_nested does not have standard signature
CODEGEN-3937 nested_exception::rethrow_nested() not supported
CODEGEN-3916 C++ header file cuchar is not provided in libc++
CODEGEN-1499 #pragma LOCATION and palign do not work together
CODEGEN-1498 Automatic library build fails when an exact library name is used
CODEGEN-1495 Compiler and assembler disagree on format for IT instruction
CODEGEN-1484 The armhex command does not handle spaces in the name of the output binary
CODEGEN-1458 Consider splitting up unified_locale.cpp to save code space
CODEGEN-1445 Compiler inserts unnecessary register copy
CODEGEN-1101 When the imaginary part of z is INFINITY, cprojf(z) is NOT equivalent to INFINITY + I * copysign(0.0, cimagf(z))
CODEGEN-1059 Compiler does not respect partial overrides in C99 designated initializers
CODEGEN-1026 Disable diagnostic 1558 (–float_operations_allowed diagnostic) in standard header files
CODEGEN-989 Should accept “LDRD R8,[R1]” in Thumb-2 mode
CODEGEN-975 Missing half-precision float conversion functions
CODEGEN-974 Missing __aeabi_read_tp
CODEGEN-972 Missing AEABI_COMPATIBILITY_MODE link-time constants
CODEGEN-967 Assembler accepts but mistranslates BLLT in v7 thumb mode
CODEGEN-966 Should allow “ADD R0, R1, #0xfff” for v6m0
CODEGEN-962 Should accept 2-operand SUB SP in Thumb1/UAL mode
CODEGEN-927 Should accept 2-operand add in ARM mode
CODEGEN-890 The .label assembler directive should not be accepted when assembling for ELF.
CODEGEN-830 __aeabi_dcmpun returns 1 for Inf and -Inf
CODEGEN-793 Ill advised enum scalar usage gets MISRA diagnostic, but similar usage of enum array does not
CODEGEN-792 Array that is correctly initialized erroneously gets a MISRA diagnostic about size not being specified
CODEGEN-753 Warning generated when using __curpc intrinsic on Thumb 2
CODEGEN-662 Double constant incorrectly converted to float changes result slightly
CODEGEN-578 MISRA 12.8 and MISRA 10.5 false positives
CODEGEN-573 Cortex-M0 library lacks uread4, etc.
CODEGEN-322 Structure is not initialized correctly when using -o2 or -o3 optimization
CODEGEN-316 The _ssat16 intrinsic allows literals in the range of 0-31, but the SSAT16 instruction only accepts values from 1-16
CODEGEN-315 _ssatl intrinsic allows 3rd argument to be 0 resulting in an assembler error.
CODEGEN-299 ARM assembler does not issue a warning for PC-relative loads when –embedded_constants=off
CODEGEN-237 Linker outputting wrong build attribute name for EABI TAG_VFP_arch on ARM targets
CODEGEN-235 Section relative ELF symbol values in partially linking object files should hold the section offset for the symbol
CODEGEN-104 Linker gives misleading warning when dot expressions used in SECTION directive for .stack section
CODEGEN-63 DWARF does not correctly represent variables stored in register pairs
CODEGEN-56 Forward reference in .space generates an internal error
CODEGEN-30 Compilers on PC will not work without TMP set

1.2 Compiler Wiki

A Wiki has been established to assist developers in using TI Embedded Processor Software and Tools. Developers are encouraged to read and contribute to the articles. Registered users can update missing or incorrect information. There is a large section of compiler-related material. Please visit:

1.3 Compiler Documentation

The “TI ARM Optimizing Compiler User’s Guide” and the “TI ARM Assembly Language User’s Guide” can be downloaded from:

1.4 TI E2E Community

Questions concerning TI Code Generation Tools can be posted to the TI E2E Community forums. The Code Composer Studio support forum can be found at:

1.5 Defect Tracking Database

The Code Generation Tools Defect Database can be searched at:

1.6 Long Term Support release

The ARM CGT v18.1.0.LTS release is a long term support (LTS) release. This release will be supported for roughly 2 years with periodic bug fix updates.

2 C++ 2014 support

As of v18.1.0.LTS, the compiler uses the C++14 version of the C++ standard. Previously, C++03 was used. See the C++ Standard ISO/IEC 14882:2014. For a description of unsupported C++14 features, see Section 5.2 of the “TI ARM Optimizing Compiler User’s Guide”.

The move to C++14 will break ABI compatibility with previous C++ RTS releases. Attempting to link old C++ object code with the new RTS will result in a link-time error. Suppressing this error will likely result in undefined symbols or undefined behavior during execution.

C ABI compatibility will not be affected by this change.

In most cases, recompiling old source code with the new RTS should be safe. However, due to the changes made in the language, some constructs will result in syntax errors. Some common issues include:

A full list can be found in Appendix C, section 2 of the C++14 standard.

3 C++ ABI Compatibility

v17.9.0.STS contains the first planned updates in preparation for the support of C++14 (International Standard ISO/IEC 14882:2014(E)). As part of this update, it is necessary to make changes which might cause errors when building C++ projects containing C++ object files compiled with older versions of the compiler.

These errors will usually include linktime errors involving undefined symbols. If you see undefined symbol errors during a link, pass the “–no_demangle” option to the compiler. If the undefined symbol’s name starts with _Z or _ZVT, then it’s possible that there is a C++ object file or library built with an older version of the tools being used. These will need to be compiled with the v18.1.0.LTS tools to work properly.

4 Support for ARM C Language Extensions (ACLE)

Beginning with the ARM CGT v17.9.0.STS release, support for ARM C Language Extensions (ACLE) as specified in the ACLE Release 2.0 document (Document number: IHI 0053C, Date of Issue: 09/05/2014) has been added for the applicable processor variants that are supported in the ARM CGT. This includes support for new ACLE attributes, intrinsics, and pre-defined symbols as detailed in the sub-sections below.

4.1 ACLE Attributes

In addition to the attributes described in the ACLE specification that the ARM CGT already supports (i.e. aligned, alias, common, nocommon, packed, section, visibility, and weak), the ARM CGT v17.9.0.STS release adds support for the “target” attribute as follows:

attribute((target(“arm”))) void myfunc()

 when applied to a function, will force the generation of ARM state code. 
 This attribute will be interpreted as if the user had specified the
 already supported "#pragma CODE_STATE(myfunc, 32)" just in front of the
 definition of the function definition of "myfunc".

attribute((target(“thumb”))) void myfunc()

 when applied to a function, will force the generation of THUMB state code. 
 This attribute will be interpreted as if the user had specified the
 already supported "#pragma CODE_STATE(myfunc, 16)" just in front of the
 definition of the function definition of "myfunc".

The ARM CGT does not support the “pcs” ACLE attribute.

4.2 ACLE Intrinsics

A new header file, arm_acle.h, has been added to the ARM CGT include subdirectory which provides declarations and/or declarations of all of the ACLE intrinsics that are now supported beginning with the v17.9.0.STS release.

The majority of ACLE intrinsics that are newly supported in this release are implemented by already supported intrinsics that may have a slightly different name. For example, the ACLE “__smulbb" intrinsic is implemented in terms of the already supported “_smulbb" intrinsic as follows:

int32_t __BUILTIN _smulbb(int32_t x, int32_t y); #define __smulbb _smulbb

The only difference being that the ACLE “__smulbb" intrinsic name has a prefix of two underscores as opposed to the name of the already supported “_smulbb" intrinsic name which has a prefix of 1 underscore.

The ARM CGT v17.9.0.STS release does not support all of the ACLE intrinsics that are included in the ACLE specification. For example, the __cls, __clsl, and __clsll ACLE intrinsics are not supported since the CLS instruction is not available on the Cortex-M or Cortex-R architectures.

Please see the arm_acle.h file for more details about exactly which ACLE intrinsics are supported and which are not. Where applicable, the declarations of ACLE intrinsics that are not supported are enclosed in comments along with a brief explanation of why the intrinsic is not supported and a reference to the appropriate section in the ACLE specification where the intrinsic is described.

4.3 ACLE Pre-Defined Symbols

The ARM CGT v17.9.0.STS compiler will now define the following ACLE pre-defined symbols:

__ARM_ACLE - defined to ‘200’ for all Cortex-M and Cortex-R processor variants supported by the ARM CGT, not defined otherwise

__ARM_ARCH - indicates which ARM architecture the compiler is generating code for:

            value   selected processor
            -----   ------------------
            '4' -mv4
            '5' -mv5e
            '6' -mv6, -mv6m0
            '7' -mv7a8, -mv7m3, -mv7m4, -mv7r4, -mv7r5

__ARM_32BIT_STATE - defined to 1 if compiler is generating code for an ARM 32-bit processor variant, otherwise undefined

__ARM_ARCH_ISA_ARM - defined to 1 if compiler is generating code for a processor variant that supports the ARM instruction set; otherwise undefined (not defined when compiling for Cortex-M processor, for example)

__ARM_ARCH_ISA_THUMB - defined to 1 if compiler is generating code for a processor variant that supports the THUMB-1 instruction set; defined to 2 if compiler is generating code for a processor variant that supports the THUMB-2 instruction set; otherwise undefined

__ARM_BIG_ENDIAN - matches endian-ness specified with compiler command-line: 1 (big-endian; default), 0 (little-endian; -me option)

__ARM_FEATURE_CLZ - defined to 1 if compiler is generating code for a processor variant that supports the CLZ instruction; otherwise undefined

__ARM_FEATURE_DSP - defined to 1 if compiler is generating code for a Cortex-M or Cortex-R processor that supports DSP instructions/intrinsics; otherwise undefined

__ARM_FEATURE_SAT - defined to 1 if compiler is generating code for a processor variant tha supports SSAT/USAT instructions/intrinsics; otherwise undefined

__ARM_FEATURE_SIMD32 - defined to 1 if compiler is generating code for a processor variant that supports all SIMD instructions/intrinsics; otherwise undefined

__ARM_FEATURE_UNALIGNED - defined to 1 if compiler is generating code for a processor variant that supports unaligned access to memory; otherwise undefined

__ARM_PCS - defined to 1 if the compiler can assumes that the default procesude calling standard for a translation unit conforms to the “base procedure call standard” as prescribed in the ARM Architecture Procedure Call Standard specification; otherwise undefined

__ARM_SIZEOF_MINIMAL_ENUM - smallest possible enum type size (1 byte for ‘packed’, 4 bytes for ‘int’ (mirroring the –enum_type=[packed|int] option where packed is the default)

__ARM_SIZEOF_WCHAR_T - size of wchar_t type: 16- (default) or 32-bits

__ARM_FP - defined to a non-zero value if the compiler can assume that floating-point hardware support is available when compiling a translation unit. The value will be a combination of:

            bit  value  precision
                        ---  -----  ---------
             1    0x2    16-bit
             2    0x4    32-bit
             3    0x8    64-bit

            For example, if --float_support=fpv4spd16 is
            selected, then __ARM_FP will have a value of
            0x6 since fpv4spd16 supports 32-bit and 16-bit
            floating-point hardware.

            If no floating-point hardware support is enabled,
            then __ARM_FP will be undefined.

__ARM_FP16_ARGS - defined to 1 if a 16-bit float type can be used for an argument and/or result; otherwise undefined

__ARM_FP16_FORMAT_IEEE - defined to 1 if the IEEE format for 16-bit floating-point (according to IEEE 754-2008 standard) is used; otherwise undefined

__ARM_PCS_VFP - defined to 1 if the default procedure calling convention is to pass floating-point arguments / return values in hardware floating-point registers

The ARM CGT v17.9.0.STS release does not support all of the ACLE pre-defined symbols that are included in the ACLE specification. For example, the __ARM_FEATURE_CRYPTO pre-defined symbol is associated with support for CRYPTO instructions which are not supported on any of the processor variants that the ARM CGT v17.9.0.STS release supports. If an ACLE pre-defined symbol in the ACLE specification is not included in the above list, then it will not be defined by the ARM CGT compiler.

5 Improved stack usage with inline functions

The new compiler improves stack usage by sharing aggregate data originally defined in inline functions. Example:

struct ARGS { int f1,f2,f3,f4,f5; };

static inline void func1() { struct ARGS a = {1, 2, 3, 4, 5}; foo(&a); }

static inline void func2() { struct ARGS b = {1, 2, 3, 4, 5}; foo(&b); }

void func3() { func1(); func2(); }

In previous compilers, if func1 and func2 are inlined, the structs a and b would not share the same stack location. This version of the compiler will now share stack memory for local aggregates defined in inline functions.